Transcript Embedded test tutorial

Janusz Rajski
Nilanjan Mukherjee
Mentor Graphics Corporation
Presenters and authors
Presenters:
Janusz Rajski
Nilanjan Mukherjee
Mentor Graphics Corporation
[email protected]
Co-author:
Jerzy Tyszer
Poznan Univ. of Technology
Tutorial ground rules
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Definition: Embedded Test refers to design-fortestability techniques where testing is
accomplished entirely or partially through on-chip
hardware.
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Disclaimer:
This tutorial is not intended to endorse or
discredit any commercial technology or product.
Audience
Everybody interested in state-of-the-art embedded test
technology, to reduce the cost of manufacturing test
In particular:
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Designers of complex integrated circuits
IP core providers and integrators
Test engineers
EDA tools developers
EDA tools users
Researchers
Project managers
Tutorial objectives
To present:
 Compelling reasons for ET adoption
 Common barriers for ET adoption
 State-of-the-art ET fundamentals and practice
 Architectures for logic and memory BIST
 Embedded deterministic techniques
 At-speed ET
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multiple-clock domain designs
multi-frequency designs
Tools for BIST synthesis automation
Application examples and case studies
Outline
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Introduction
Embedded stimuli generators
Compactors of test responses
Logic BIST
Deterministic forms of embedded test
Embedded at-speed test
Comparison of scan/ATPG, logic BIST and
embedded forms of deterministic test
BIST schemes for embedded memory arrays
Summary of embedded test
Design characteristics
CPU core
DSP core
ASIC
IP core
ASIC
Memory
Memory
Memory
I/0
IP core
PLL
Memory
Memory
ASIC
Analog
ASIC
System on Chip characteristics
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System architecture
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Microprocessors, DSP cores
 Buses, peripherals, memory
 ASIC portion
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Structures: Logic, memory, analog
Multiple embedded memories:
DRAM, Flash, CAM
Analog and mixed signal: PLLs,
clock recovery
Field programmable logic
RF cores: wireless receivers
IP cores and reusable blocks
available from multiple vendors
Design efficiency achieved by
hierarchical core-based design style
CPU core
DSP core
ASIC
IP core
Memory
ASIC
Memory
I/0
IP core
PLL
Memory
Memory
Memory
ASIC
Analog
ASIC
New defects
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Geometries shrink at 30% every three years
Defect sizes do not shrink in proportion
Increase of wiring levels from 6 to 9
Interconnect delays dominate
Gate delays reduced
Bridging faults
Sematech S-121
“Test Method Evaluation –Key Findings &
Conclusions”
Objective:
 Evaluate various test methodologies
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Large sample size
Extensive data collection & analysis
[Sematech, 1998]
Sematech S-121
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Device 116K equivalent gates
0.45 µm L effective (0.8 µm drawn)
50 MHz operating speed
249 signal I/Os
3 metal levels
Full LSSD Scan plus JTAG boundary scan
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8 Chains, 5,280 master/slave LSSD latches (10,560
total latches)
Sample size 20,000 units
Test methods:
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Stuck-at faults, Functional tests, Transition delay
faults & IDDQ
Sematech S-121
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Package test results
(pre Burn-in)
SAF - 99.5% coverage
(8300 patterns)
FUNC - 52% SAF coverage
(532K cycles)
Delay - 90% Transition coverage
(15232 patterns)
IDDQ - >96% pseudo SAF coverage
(195 patterns)
IDDQ
1463
7
FUNC
6
1
0
13
8
1251
36
Delay
52
14
34
IDDQ
SAF
6
1
FUNC
S-121 Conclusions
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All test methods detected unique defects
Near 100% SAF coverage missed many defects
Large defect coverage overlap between SAF & Delay
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IDDQ threshold setting significantly affects yield
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98% of the IDDQ fails survived burn-in
Many (bridging) defects detected only by IDDQ
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SAF are a subset of Transition faults
But diminishing IDDQ effectiveness in DSM
Some Functional tests are still required
Opportunity to optimize test coverage levels & capital
Process Shrinks vs. Defect Types
Defect Pareto 350 nm
Unknown
BridgeM1-2
Via break
Bridge M2
Bridge M4
Break trans
Bridge Poly M2
Bridge M3
Bridge M1-3
Bridge poly M1
Bridge M3-4
Open Poly
Open Contact
Bridge M1
Unknown Br
Break M3
Bridge Poly M2
Break M2
Bridge M3-4
Break M1
Bridge Poly M4
Bridge Poly
350 nm Process 5 million Transistors
Al
4-5 Levels
W Plugs
Oxide
Dielectric
A Transistor
Process Shrinks vs. Defect Types
Defect Pareto 100 nm
100 nm Process -- 250 million transistors
Unknown
?
Cu
(8 Levels)
Low-K
Dielectric
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Defect distribution change
with process
Cu
Plugs
A Transistor
Defects vs. Fault Coverage
 Wired
“AND” & “OR” models
are not sufficient
 Speed limiting defects
 Frequency of bridging defects
is increasing
 Need to drive ATE & modeling
requirements from the defects
to be detected
 Will drive need for more scan
vectors
Bridge Defect Observed Resistance
.18 um
.25 um
Test chip FA results
1
10
100
1000
K-Ohms
Increasing defect populations causing
more VDD, Temp, & freq sensitive device fails
[M. Rodgers , et. al. DAC 2000]
Quality requirements
Y
Escapes
1-p
Faults
detected
p
1-Y
Quality requirements
Escapes = (1 - Y)(1 - p)
0.01
0.009
0.008
Yield = 0.9
0.007
0.006
Yield = 0.1
0.005
0.004
0.003
0.002
0.001
0
p
0.990 0.991 0.992 0.993 0.994 0.995 0.996 0.997 0.998 0.999 1.000
Fault models
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Stuck-at-0 and stuck-at-1
Transitions
Path delay
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Multiple detects
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VDD
Very high test quality
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Very high fault coverage
Wide range of fault models
•
stuck-at
• transition
• path delay
• at-speed testing
• multiple detects
• bridging
• defect based
• cross-talk effects
• ... fading IDDQ
Coverage
Escapes
High-performance MPU/ASIC gate count
Gate count
300
250
ITRS Roadmap 2001
200
150
100
50
0
2001
2002
2003
2004
2005
2006
2007
Scan chains
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The pattern count for transition faults may reach 20,000
Scan test
Scan output
channels
Scan input
channels
Primary outputs
Primary inputs
ATE
ATE cost
Tester cost = b + S m p
b - base cost (zero pins)
m - incremental cost per pin
p - number of pins
Test cost can be
$0.05/second
b [ K$ ]
m[$]
p
High performance
ASIC / MPU
250 - 400
2700 - 6000
512
DFT tester
100 - 350
150 - 650
512 - 2500
Low performance
Microcontroller
200 - 350
1200 - 2500
256 - 1024
Volume of scan test data
Test cycles =
Scan cells
 Patterns
Scan chains
...
Scan test time
Scan cells
Patterns

Test time =
Scan chains Frequency
...
Scan test cost
Gate count
10M
500,000
Scan cells
Scan chains
32
15,625
Cells per scan
Padding ratio
1.4
21,875
Longest scan chain
Scan patterns
20K
437.5M
Cycles
Shift frequency
20 MHz
21.9s
Scan test time
Vector memory
64MV
6
Passes
Reload penalty
2s
12.0s
Reload time
Insertions
4
87.5s
Time pre device
Tester rate
0.05$
4.4$
Cost per device
More
High-performance MPU/ASIC
Required ATE memory
Gigabits/channel
12
10
32 channels
20,000 patterns
8
6
4
2
0
2001
2002
2003
2004
2005
2006
2007
High-performance MPU/ASIC
Scan test time
seconds
120
100
100 MHz scan shift
80
60
40
20
0
2001
2002
2003
2004
2005
2006
2007
ATE accuracy vs. device speed
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Tester accuracy will improve from 200 ps to 175 ps by 2012
Clock period will decrease to 330 ps
Margin of error for ATE approaches 50% clock period
600
500
400
Device period
300
200
ATE accuracy
100
Accuracy
required
0
2001
2002
2003
2004
2005
2006
2007
Requirements for Embedded Test
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Increasing device complexity, operating speed,
and new fault models stress conventional scan
based test:
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Exploding volume of test data
Increasing scan test time, and
Escalating scan test cost
Embedded Test is required to:
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Generate most of the test data on-chip
Compacting test responses on-chip, and
Providing on-chip control for at-speed test
Very low cost
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Dramatically reduced volume of test data (10-100X)
Dramatically reduced scan test time (10-400X)
ATE Memory 35
[Mvectors]
30
16 scan chains
5k vectors
2s handler/index time
1 test
10MHz scan shift
10X
2M gates
Scan/ATPG
25
20
15
10
5
10X
0
0
1
2
3
4
5
6
7
Scan test time[s]
Long term scalability
100X increase
in 10 years!
100
10
Volume in
conventional DFT
1
0.1
0
1.5
3
4.5
6
years
7.5
9
10.5
Radical compression is required!
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Immediate 5-10X
compression
Compression
ahead of volume
for 10 years
100
Compression factor
10
Volume in
conventional DFT
1
0.1
0
1.5
3
4.5
6
years
7.5
9
10.5
Radical compression is required
100
Compression
should be
ahead of
Moore’s law for
10 years!
Compression factor
10
Volume in
conventional DFT
1
Compressed
volume
0.1
0
1.5
3
4.5
years
6
7.5
9
10.5