Transcript Unit 9 Multiplexers, Decoders, and Programmable Logic Devices

Unit 9 Multiplexers, Decoders,
and Programmable Logic
Devices
Fundamentals of Logic Design
by Roth and Kinney
9.1 Introduction
• SSI—small scale integration
– NAND,NOR,AND, and OR, inverters, and flip-flops (14 gates, 6 inverters, 1 or 2 flip-flops); in a single pkg
• MSI—medium-scale integration
– Adders, Multiplexers, Decoders, Registers, and
Counters(12-100 gates—in a single package)
• LSI—large –scale integration (memories or
microprocessors) (100-few thousand gates; in a
single package)
• VLSI—very large scale integration (memories or
microprocessors) (several thousand gates or
more in a single package).
9.1 (cont.)
• Cost tends to decrease when LSI and
VLSI circuits are used (wiring, mounting,
and maintaining designs.)
• Design trends—LSI and VLSI.
9.2 Multiplexers
• Data inputs and control inputs.
• The control inputs are used to select one
of the data inputs.
– See Figures 9-1 and 9-2.
– Note that the output Z of the 4 x 1 multiplexer
is Z= A’B’I0 + AB’I1 +AB’I2 + ABI3
9.2 (cont.)
• Equation 9-2 –shows output Z for an 8x1
multiplexer.
• Figure 9.3—Logic diagram for 8 to 1 Mux.
– NAND or NOR gates can be used .
– 2-levels shown
• Figure 9-4—Multi-Level 8 to 1 Mux using
NANDS.
• Figure 9-9 illustrates the MUX used to
implement a simple function.
9.3 Three-State Buffers
• A simple buffer can be used to increase
the driving capability of a gate output.
– See Figure 9.10, page 266.
• A three-state (tri-state) buffer allows the
outputs of two or more gates to be
connected together.
– See Figure 9-11; when the control “B” is 0 the
output will have a high inpedence.
9.4 Decoders and Encoders
• Figure 9-17 3-5o-8 line decoder
– Generates all of the minterms.
– Only one output will be high for each
combination of the input variables.
9.4 (cont.)
• Figure 9-18 A 4 –to- 10 line decoder
(7442)
– (a) Logic diagram
– (b) Block diagram
– (c) Truth Table (one output will be a 0)
– Binary coded decimal are used as the input.
9.4 (cont.)
• An encoder performs the inverse function
of a decoder (Figure 9.20).
9.5 Read-Only Memories
• ROM—read only memory; used to store
data.
– Figure 9-21 – An 8-word x 4 bit ROM.
• (a) Block Diagram
• (b) Truth Table
9.6 Programmable Logic Devices
• PLD—programmable logic device– a
digital integrated circuit capable of being
programmed to provide a variety of
different logic functions.
• PLA—programmable logic array
– Similar in function to a ROM
9.7 Complex Programmable Logic
Devices
• CPLD—many PLAs can be placed today
on a single chip.
• Figure 9-34—Architecture of Xilinx
XCF3064XL CPLD.
9.8 Field-Programmable Gate
Arrays
• FPGA—an IC that contains an array of
identical logic cells (configurable logic
blocks) with programmable
interconnections. (See Figure 9-36)
– Array of CLBs is surrounded by I/O blocks.
– The I/O blocks connect the CLBs with the pins
of the FPGA chip.
– The space between CLBs is used to route
the connections between the CLB outputs and
inputs.
9.8 (cont.)
• Simplified CLB—Figure 9-37
– 2 “function generators” of logic lookup Tables
(LUTs)
• LUTs—reprogrammable ROMs (16 1-bit words
• LUTs—store the truth table of the function being
implemented.
– 2 flip-flops ( outputs XQ and YQ)
– Multiplexors (for routing signals)
• H chooses between F and G.
• Selects combinational logic outputs, X and Y.