Transcript Document

Programmable Logic Devices
 Read
Only Memorys (ROM)
 Programmable Logic Arrays (PLA)
 Programmable Array Logics (PAL)
 Field Programmable Gate Arrays (FPGA)
Read MK 124-132
Implementation Options for Digital Logic
 Assembly
of SSI and MSI parts on PC boards.
» mostly obsolete; still useful when just a few parts needed
 Programmable
Logic Devices (PLD)
» variety of types, with different size and performance
characteristics; largest have over 106 gate “equivalents”
» CAD tools enable simulation and automate device
programming
 Application
Specific Integrated Circuits (ASIC)
» design methods similar to PLDs
– HDLs and simulation with synthesis using standard cell library
– plus physical design - placement of logic components and routing
» can augment with custom design of critical components
» higher performance, greater logic density
» custom IC fabrication -- suitable for high production volumes
8.‹#› - Jon Turner - 4/9/2016
Programmable Logic Devices
 Simple
logic arrays
» implement 2 level logic circuits (AND/OR)
» based on regular array structure
» several types
– Read Only Memories (ROMs and PROMs)
– Programmable Logic Array (PLA)
– Programmable Array Logic (PAL)
 Field
Programmable Gate Arrays (FPGA)
» many copies of common building block
» each block can be configured for different logic functions and
typically includes a flip flop and a 4 input function generator
» programmable interconnect
» often includes SRAM blocks
» largest FPGAs have about 100K flip flops, 100K function
generators and 10 Mb of SRAM
8.‹#› - Jon Turner - 4/9/2016
Read-Only Memory
 Any
random access memory can implement logic.
» store the logic function’s truth table in memory
» example: use 4 bit RAM to get 2 input AND by storing 0 at
locations 00, 01, 10 and 1 at location 11
» with 2m words of 1 bit each can implement any logic function
with m inputs
» memory with 2m words of w bits each can implement w
different logic functions of same m inputs
 Read-Only
Memory (ROM) operates like a random
access memory, but cannot be written to.
» stored data is determined when device is manufactured
» higher density and faster than comparable RAMs
» non-volatile storage - data retained when power is off
» programmable ROMs are written with PROM programmer
8.‹#› - Jon Turner - 4/9/2016
Implementation of ROMs
ROM can be implemented using
orthogonal arrangement of wires.
0
1
» optional connection at each intersection
» decoder puts logic ‘1’ on exactly one of
the horizontal wires - this can be detected
at output if connection present

inputs
2
Some PROMs are configured by
breaking connections.
Other PROMs can be erased and
reprogrammed (EPROMs).
8.‹#› - Jon Turner - 4/9/2016
3
4
5
6
» high voltage placed across one input and
one output at a time
» high current flow causes “fuse” at
intersection to “blow”

decoder

7

stored functions
» m(0,1,3,4,6), m(0,1,3,5,7),
m(2,3,6,7), m(0,3,4,6)
Programmable Logic Arrays
configurable
connection x0x2x3x4x5
x0x1x2x3x4x5
x0x2x4x5
x0x1x2x5
configurable
connection
x0x4x5
x 1x2x3x4
x0 x1 x2 x3 x4 x5
 PLAs
z0
z1
z2
z3 = x0x1x2x3x4x5 + x0x1x2x5
have configurable “AND-plane” & “OR-plane”.
 Can implement any 2-level AND-OR circuit.
 Efficient physical implementation in CMOS.
8.‹#› - Jon Turner - 4/9/2016
Programmable Array Logic
x0x2x3x4x5
x0x1x2x3x4x5
x0x2x4x5
configurable
connection
x0x1x2x5
x0x4x5
x1x2x3x4
x0 x1 x2 x3 x4 x5
 PAL
z0
z1
z2 = x0x2x3x4x5 + x0x1x2x3x4x5
is similar to PLA but fixed OR-plane.
 Simpler to program and cheaper implementation.
 Limited number of terms in each output.
8.‹#› - Jon Turner - 4/9/2016
Comparison of PROMs, PLAs & PALs
 Can
view PROMs and PALs as restricted forms of PLA.
» PROMs are logically equivalent to PLA with AND-plane that
generates all minterms and configurable OR-plane
» PAL is logically equivalent to PLA with fixed OR-plane in
which each output is the OR of a subset of the ANDs
 Different
implementations means different capabilities.
» so, one needs to match device capabilities to the
characteristics of logic equations being generated
» consider number inputs & outputs, total number of different
terms (PLAs), number of different terms per output (PALs)
– for given number of inputs/outputs, PROMs most flexible
» performance characteristics and cost also differ
 Most
parts include flip flops, for implementing
sequential circuits.
8.‹#› - Jon Turner - 4/9/2016
Field Programmable Gate Arrays
 FPGAs
can be used to construct more complex circuits.
 Chip contains a large number (tens of thousands) of
configurable logic building blocks.
» typically each block includes a 4 input function generator, a
flip flop and some “glue” logic
» CAD tools map high level circuit to basic blocks, configuring
function generators & other configurable elements as needed
 Programmable
interconnect used to wire logic blocks.
» wire segments connected to logic blocks and to other wire
segments by configurable switches
» CAD tools determine switch configuration needed to provide
right connectivity
 CAD
tools perform mapping, placement, routing.
» routing information used in timing analysis & simulation
8.‹#› - Jon Turner - 4/9/2016
Xilinx FPGA Organization
switch matrix
wire segments
configurable logic blocks (CLB)
IO blocks (IOB)
 CLBs
can be connected to “passing” wires.
 Wire segments connected by switch matrix.
 Long wire segments used to connect distant CLBs.
 Configuration information stored in SRAM bits that are
loaded when power turns on.
8.‹#› - Jon Turner - 4/9/2016
Configuring Logic
A
B
C
0
1
2
3
4
5
6
7
0
0
1
0
1
1
1
0
f(A,B,C)
0
1
2
3
0 1
1
configuration memory
 Lookup
table implements logic
functions.
 Multiplexors and pass
transistors implement routing.
 Switch matrix contains configurable
clusters of pass transistors.
» provides wide variety of routing options
8.‹#› - Jon Turner - 4/9/2016
Xilinx Configurable Logic Block
Main
Function
Generators
G1
G2
G3
G4
Clock Edge
Select
CLK EC
S/R
Y
S/R C
Set/Reset
Control
LUT4
D
PRE
>
DIN
YQ
EC CLR
H1
F1
F2
F3
F4
LUT3
Clock Enable
Control
1
D
LUT4
PRE
>
XQ
EC CLR
Main
Function
Generators
8.‹#› - Jon Turner - 4/9/2016
1
S/R C
Flip Flop
X
Implementing Serial Adder in CLB
CLK
Sum
Function
A
B
0
LUT4
ABCarry
EC
S/R
Sum
S/R C
0
01101001
01101101
D
DIN
01
H1
LUT3
PRE
Carry
>
0
EC CLR
1
State
Flip Flop
1
LUT4
EN
00000000
00010111
D
>
(AB+ACarry
+BCarry)EN
Carry
Function
PRE
XQ
EC CLR
1
S/R C
X

Second flip flop still available and LUT3 partially available.
8.‹#› - Jon Turner - 4/9/2016