Transcript Diapositiva 1 - Indico

Introductory remarks
v. 1.0
• three stations, each station 60x27 mm2 , Si-matrix formed by 18000 300x300 mm pixels
• thickness of the detector: 200 mm
• operated in vacuum
• sensor p-in-n
• stations replaced after one year (or a substantial part of ) of data taking
beam
Sept. 29th, 2010
F. Marchetto
(INFN-Torino)
• beam intensity: 750 MHz -> <Dt> = 1.14 nsec
• association between incoming and outgoing track based on a time resolution of 150 psec
and a spatial resolution of ~100 mm (from the pixel dimension) and a angular resolution of
16 mrad -> corresponding to ~2 mm of mismatch (closest distance of approach between
the two tracks).
• all the quoted number represent
rms
• time resolution per hit -> 200 psec corresponds to 150 psec on a track (typically 3hits/track)
Basically:
• three stations, each 60x27 mm2 and 18000 pixels (300x300 mm)
• each station: 10 chips, each chip reads 40 columns x 45 pixels = 1800 pixels
Chip dimensions: 12 (W) x 13.5 (L) mm2 to cover the active area of
the detector plus extra length for the end-of-column logic and for the
serializer
Max linear dimension of the chip: 20 mm
1. Front end: two options to correct for the time walk
• Time-over-Threshold and DLL at the end of the column (EOC)
•
CFD and TDC on the pixel (P-TDC)
2. First submission of building blocks in CMOS 130 nm: beginning of
2007
3. Design of a first prototype to be bonded to a sensor (small scale)
started beginning of 2008.
4. Design review October 2008: P. Moreira, C. Mester, K. Kloukinas, K.
Wyllie, M. Campbell, D. Breton (LAL-Orsay): summary can be found
in
http://indico.cern.ch/getFile.py/access?contribId=0&resId=1&material
Id=slides&confId=43362
5. Submission of both prototypes March 2009
6. Electrical Test started in Fall 2009 for the ToT (EOC) option, later in
Spring 2010 for the P-TDC option
Personal remarks (not necessarily shared by the GTK-Working group)
• Two option-approach was a good idea that allowed to broaden our view of the
challenging problem we are facing and at the same time we maximized the human
resources within the GTK-WG.
• If we would foresee a development with several prototype iterations very likely
both solutions could lead to a detector working within specifications, but…
• in front of us, we expect to have not more than one prototype iteration, followed by
the engineering runs (one or two at most).
• the work done by the designers has been of very high level, in moving ahead we
need to share doubts, problems, and any technical detail with a larger community.
This is why we are here, and for this we are extremely grateful to each expert of the
committee.
• My concerns are related to the uncertainty in extending from the limited size
prototype to the full scale final chip.
•Basically, which architecture looks more suitable to be integrated into a large chip?
• Do you see possible hidden (so far) complication that could eventually pop up?
Thanks and have a fruitful review