Transcript CS 140 Lecture 6

CS 140L Lecture 1
CK Cheng
CSE Dept.
UC San Diego
1
Outlines
•
•
•
•
•
Administration
Lab. Overall View
FPGA Architecture
Transistors
Gates
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Administration
Web site:
http://www.cse.ucsd.edu/classes/sp09/cse140L/
WebBoard:
http://webboard.ucsd.edu
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Administration
Instructor: CK Cheng, CSE2130,
[email protected], 858 534-6184
Teaching Assistants:
• Thomas Weng, [email protected]
• Renshen Wang, [email protected]
• Chengmo Yang, [email protected]
• Mingjing Chen, [email protected]
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Administration
Schedule
• Lecture: 2:00-2:50PM, W, Center 212.
• Discussion: 3:00-3:50PM, W, Center 212.
• Office hours: 10:30-11:30AM, TTh, CSE
2130.
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Administration
Textbook
• Digital Design and Computer Architecture,
David Money Harris and Sarah L. Harris,
published by Morgan Kaufmann, 2007.
Hardware
• Altera DE1 Education Kit
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Administration
Labs (68%): computer simulations, board
demonstration, report write-up. One report per
group.
• 1. Combinational Circuit Designs
• 2. The Specification and Usage of Flip-Flops
• 3. Finite State Machines
• 4. System Design using Datapath and Control
Subsystems
Final (30%): 3:00-4:30PM F6/12
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Overall View of Labs
Behavior description
C, System C,
Verilog, VHDL
Register Transfer Level
Verilog, VHDL
Logic Synthesis
Netlist of Logic
Placement, Routing
Physical Layout
Mask Fabrication
FPGAs
1. Data Representation
2. Synthesis: Logic, Physical Layout
3. Analysis: Functional, Timing Verification
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FPGAs (Field Programmable Gate Arrays)
Programmable Logic Block
Switches
Switch Matrix
Wiring Channels
-SRAM based (Flash memory)
-Antifuse
Disadvantages: Penalty on area, density, speed
Advantages: Flexibility, low startup costs, low risk,
revisions without changing the hardware
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Transistors: Silicon
• Transistors are built out of silicon, a semiconductor
• Pure silicon is a poor conductor (no free charges)
• Doped silicon is a good conductor (free charges)
– n-type (free negative charges, electrons)
– p-type (free positive charges, holes)
Free electron
Si
Si
Si
Si
Si
Si
Si
Si
Si
Si
Si
Si
Si
Silicon Lattice
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Free hole
Si
Si
Si
As
Si
Si
B
Si
Si
Si
Si
-
+
n-Type
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+
-
Si
Si
Si
p-Type
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MOS Transistors
• Metal oxide silicon (MOS) transistors:
– Polysilicon (used to be metal) gate
– Oxide (silicon dioxide) insulator
– Doped silicon
source
gate
drain
Polysilicon
SiO2
n
n
p
substrate
gate
source
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Elsevier
drain
1-<11>
nMOS
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Transistors: nMOS
Gate = 0, it is OFF (source and
drain are disconnected)
Gate = 1, it is ON (channel
between source and drain)
Source= 0 => Drain=0
Source=1 => Drain=0.8 (Poor one)
source
drain
source
gate
gate
VDD
drain
GND
n
n
p
n
channel
p
substrate
GND
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+++++++
-------
n
substrate
GND
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Transistors: pMOS
• pMOS transistor is just the opposite
– ON when Gate = 0
• Source =0 => Drain = 0.2 (Poor zero)
• Source =1 => Drain = 1
source
gate
– OFF when Gate = 1
drain
Polysilicon
SiO2
p
p
n
substrate
gate
source
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drain
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Transistor Function
d
nMOS
pMOS
g=1
d
d
OFF
g
ON
s
s
s
s
s
s
g
OFF
ON
d
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g=0
d
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d
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Transistor Function
• nMOS transistors pass good 0’s, so connect source
to GND
• pMOS transistors pass good 1’s, so connect source
to VDD
pMOS
pull-up
network
inputs
output
nMOS
pull-down
network
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CMOS Gates: NOT Gate
NOT
A
VDD
Y
A
Y=A
A
0
1
Y
1
0
P1
Y
N1
GND
A
P1
N1
Y
0
1
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CMOS Gates: NOT Gate
NOT
A
VDD
Y
A
Y=A
A
0
1
Y
1
0
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P1
Y
N1
GND
A
P1
N1
Y
0
ON
OFF
1
1
OFF
ON
0
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CMOS Gates: NAND Gate
NAND
A
B
P2
Y
Y
Y = AB
A
0
0
1
1
B
0
1
0
1
Y
1
1
1
0
P1
A B P1
0 0
0 1
1 0
1 1
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A
N1
B
N2
P2
N1
N2
Y
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CMOS Gates: NAND Gate
NAND
A
B
P2
Y
Y
Y = AB
A
0
0
1
1
B
0
1
0
1
Y
1
1
1
0
P1
A
N1
B
N2
A B P1
0 0 ON
0 1 ON
P2
N1
N2
Y
ON OFF OFF 1
OFF OFF ON 1
1 0 OFF ON ON
1 1 OFF OFF ON
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OFF 1
ON 0
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CMOS Gate Structure
pMOS
pull-up
network
inputs
output
nMOS
pull-down
network
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NOR Gate
How do you build a three-input NOR gate?
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NOR3 Gate
Three-input NOR gate
A
B
C
Y
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Other CMOS Gates
How do you build a two-input AND gate?
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Other CMOS Gates
Two-input AND gate
A
B
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Y
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Transmission Gates
• nMOS pass 1’s poorly
• pMOS pass 0’s poorly
• Transmission gate is a better switch
– passes both 0 and 1 well
• When EN = 1, the switch is ON:
EN
A
B
EN
– EN = 0 and A is connected to B
• When EN = 0, the switch is OFF:
– A is not connected to B
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Noise
• Anything that degrades the signal
– E.g., resistance, power supply noise, coupling
to neighboring wires, etc.
• Example: a gate (driver) could output a 5
volt signal but, because of resistance in a
long wire, the signal could arrive at the
receiver with a degraded value, for
Noise
example, 4.5 volts
Driver
5V
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Receiver
4.5 V
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The Static Discipline
• Given logically valid inputs, every circuit
element must produce logically valid
outputs
• Discipline ourselves to use limited ranges
of voltages to represent discrete values
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Logic Levels
Driver
Receiver
Output Characteristics
Logic High
Output Range
VO H
VDD
Input Characteristics
Logic High
Input Range
NMH
Forbidden
Zone
VO L
NML
Logic Low
Output Range
GND
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VIH
VIL
Logic Low
Input Range
Noise Margins
Driver
Receiver
Output Characteristics
Logic High
Output Range
VO H
VDD
Input Characteristics
Logic High
Input Range
NMH
Forbidden
Zone
VO L
NML
Logic Low
Output Range
GND
NMH = VOH – VIH
NML = VIL – VOL
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VIH
VIL
Logic Low
Input Range
DC Transfer Characteristics
Ideal Buffer:
Real Buffer:
V(Y)
A
V(Y)
Y
VDD
VOH
VOH VDD
Unity Gain
Points
Slope = 1
VOL
VOL 0
V(A)
VDD / 2
V(A)
0
VDD
VIL VIH
VIL, VIH
NMH = NML = VDD/2
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NMH , NML < VDD/2
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VDD
DC Transfer Characteristics
A
Y
V(Y)
Output Characteristics
VDD
VOH
VO H
VDD
Input Characteristics
NMH
Forbidden
Zone
Unity Gain
Points
Slope = 1
VOL
VO L
NML
V(A)
0
VIL
VIH
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VDD
GND
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VIH
VIL
VDD Scaling
• Chips in the 1970’s and 1980’s were
designed using VDD = 5 V
• As technology improved, VDD dropped
– Avoid frying tiny transistors
– Save power
• 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, 1.0 V,
…
• Be careful connecting chips with different
supply voltages
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Logic Family Examples
Logic Family
VDD
VIL
VIH
VOL
VOH
TTL
5 (4.75 - 5.25)
0.8
2.0
0.4
2.4
CMOS
5 (4.5 - 6)
1.35
3.15
0.33
3.84
LVTTL
3.3 (3 - 3.6)
0.8
2.0
0.4
2.4
LVCMOS
3.3 (3 - 3.6)
0.9
1.8
0.36
2.7
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Power Consumption
• Power = Energy consumed per unit time
• Two types of power consumption:
– Dynamic power consumption
– Static power consumption
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Dynamic Power Consumption
• Power to charge transistor gate capacitances
• The energy required to charge a
capacitance, C, to VDD is CVDD2
• If the circuit is running at frequency f, and
all transistors switch (from 1 to 0 or vice
versa) at that frequency, the capacitor is
charged f/2 times per second (discharging
from 1 to 0 is free).
Pdynamic = ½CVDD2f
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Static Power Consumption
• Power consumed when no gates are
switching
• It is caused by the quiescent supply current,
IDD, also called the leakage current
• Thus, the total static power consumption is:
Pstatic = IDDVDD
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Power Consumption Example
• Estimate the power consumption of a
wireless handheld computer
–
–
–
–
VDD = 1.2 V
C = 20 nF
f = 1 GHz
IDD = 20 mA
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Power Consumption Example
• Estimate the power consumption of a
wireless handheld computer
–
–
–
–
VDD = 1.2 V
C = 20 nF
f = 1 GHz
IDD = 20 mA
P = ½CVDD2f + IDDVDD
= ½(20 nF)(1.2 V)2(1 GHz) + (20 mA)(1.2 V)
= 14.4 W
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