Transcript CMOS VLSI Design CMOS VLSI Design 4th Ed. 2

Lecture 5:
DC &
Transient
Response
Outline






Pass Transistors
DC Response
Logic Levels and Noise Margins
Transient Response
RC Delay Models
Delay Estimation
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
2
Pass Transistors
 We have assumed source is grounded
 What if source > 0?
VDD
– e.g. pass transistor passing VDD
VDD
 Vg = VDD
– If Vs > VDD-Vt, Vgs < Vt
– Hence transistor would turn itself off
 nMOS pass transistors pull no higher than VDD-Vtn
– Called a degraded “1”
– Approach degraded value slowly (low Ids)
 pMOS pass transistors pull no lower than Vtp
 Transmission gates are needed to pass both 0 and 1
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
3
Pass Transistor Ckts
VDD
VDD
VDD
VDD
VDD
VDD
Vs = VDD-Vtn
VDD-Vtn VDD-Vtn
VDD
VDD-Vtn
VDD-Vtn
Vs = |Vtp|
VDD
VDD-2Vtn
VSS
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
4
DC Response
 DC Response: Vout vs. Vin for a gate
 Ex: Inverter
– When Vin = 0
->
Vout = VDD
– When Vin = VDD
->
Vout = 0
VDD
– In between, Vout depends on
Idsp
transistor size and current
Vin
Vout
– By KCL, must settle such that
Idsn
Idsn = |Idsp|
– We could solve equations
– But graphical solution gives more insight
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
5
Transistor Operation
 Current depends on region of transistor behavior
 For what Vin and Vout are nMOS and pMOS in
– Cutoff?
– Linear?
– Saturation?
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
6
nMOS Operation
Cutoff
Linear
Saturated
Vgsn < Vtn
Vin < Vtn
Vgsn > Vtn
Vin > Vtn
Vdsn < Vgsn – Vtn
Vout < Vin - Vtn
Vgsn > Vtn
Vin > Vtn
Vdsn > Vgsn – Vtn
Vout > Vin - Vtn
VDD
Vgsn = Vin
Vdsn = Vout
5: DC and Transient Response
Vin
Idsp
Vout
Idsn
CMOS VLSI Design 4th Ed.
7
pMOS Operation
Cutoff
Linear
Saturated
Vgsp > Vtp
Vin > VDD + Vtp
Vgsp < Vtp
Vin < VDD + Vtp
Vdsp > Vgsp – Vtp
Vout > Vin - Vtp
Vgsp < Vtp
Vin < VDD + Vtp
Vdsp < Vgsp – Vtp
Vout < Vin - Vtp
VDD
Vgsp = Vin - VDD
Vdsp = Vout - VDD
5: DC and Transient Response
Vtp < 0
Vin
Idsp
Vout
Idsn
CMOS VLSI Design 4th Ed.
8
I-V Characteristics
 Make pMOS is wider than nMOS such that bn = bp
Vgsn5
Idsn
Vgsn4
Vgsn3
Vgsn2
Vgsn1
-Vdsp
Vgsp1
Vgsp2
-VDD
0
VDD
Vdsn
Vgsp3
Vgsp4
-Idsp
Vgsp5
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
9
Current vs. Vout, Vin
Idsn, |Idsp|
Vin0
Vin5
Vin1
Vin4
Vin2
Vin3
Vin3
Vin4
Vin2
Vin1
Vout
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
VDD
10
Load Line Analysis
 For a given Vin:
– Plot Idsn, Idsp vs. Vout
– Vout must be where |currents| are equal in
Idsn, |Idsp|
Vin0
Vin5
Vin1
Vin4
Vin2
Vin3
Vin3
Vin4
Vin2
Vin1
Vout
5: DC and Transient Response
VDD
Vin
Idsp
Vout
Idsn
VDD
CMOS VLSI Design 4th Ed.
11
Load Line Analysis
 Vin = 0V
0.4V
0.6V
0.8V
.2V
DD DD
DD
|
Idsn
dsn, |Idsp
dsp
Vin0
Vin5
in5
Vin1
Vin4
Vin2
Vin3
Vin3
Vin4
Vin2
Vin1
in0
Vout
out
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
VDD
DD
12
DC Transfer Curve
 Transcribe points onto Vin vs. Vout plot
Vin0
Vin5
Vin1
Vin4
Vin2
Vin3
Vin3
Vin4
Vin2
Vin1
Vout
5: DC and Transient Response
VDD
Vin0
Vin1
Vin2
B
A
Vout
C
Vin3
D
0
VDD
Vtn
VDD/2
Vin4
E
VDD+Vtp
Vin5
VDD
Vin
CMOS VLSI Design 4th Ed.
13
Operating Regions
 Revisit transistor operating regions
VDD
Vin
Region
nMOS
pMOS
A
Cutoff
Linear
B
Saturation
Linear
C
Saturation
Saturation
D
Linear
Saturation
E
Linear
Cutoff
Vout
VDD
A
B
Vout
C
D
0
Vtn
VDD/2
E
VDD+Vtp
VDD
Vin
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
14
Beta Ratio
 If bp / bn  1, switching point will move from VDD/2
 Called skewed gate
 Other gates: collapse into equivalent inverter
VDD
bp
 10
bn
Vout
2
1
0.5
bp
 0.1
bn
0
Vin
5: DC and Transient Response
VDD
CMOS VLSI Design 4th Ed.
15
Switching Threshold
1.8
1.7
1.6
1.5
M
V (V)
1.4
1.3
1.2
1.1
1
0.9
0.8
10
0
10
W /W
p
5: DC and Transient Response
1
n
CMOS VLSI Design 4th Ed.
16
Inverter Gain
0
-2
-4
gain
-6
-8
-10
-12
-14
-16
-18
0
0.5
1
1.5
2
2.5
V (V)
in
CMOS VLSI Design 4th Ed.
Gain as a function of VDD
2.5
0.2
2
0.15
Vout(V)
Vout (V)
1.5
0.1
1
0.05
0.5
Gain=-1
0
0
0.5
1.5
1
2
2.5
0
0
V (V)
0.05
0.1
V (V)
in
in
CMOS VLSI Design 4th Ed.
0.15
0.2
Simulated VTC
2.5
2
Vout(V)
1.5
1
0.5
0
0
0.5
1.5
1
V (V)
in
CMOS VLSI Design 4th Ed.
2
2.5
Impact of Process Variations
2.5
2
Good PMOS
Bad NMOS
Vout(V)
1.5
Nominal
1
Good NMOS
Bad PMOS
0.5
0
0
0.5
1
1.5
2
Vin (V)
CMOS VLSI Design 4th Ed.
2.5
Noise Margins
 How much noise can a gate input see before it does
not recognize the input?
Output Characteristics
Logical High
Output Range
VDD
Input Characteristics
Logical High
Input Range
VOH
NMH
VIH
VIL
Indeterminate
Region
NML
Logical Low
Output Range
VOL
Logical Low
Input Range
GND
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
21
Logic Levels
 To maximize noise margins, select logic levels at
– unity gain point of DC transfer characteristic
Vout
Unity Gain Points
Slope = -1
VDD
VOH
b p/b n > 1
Vin
VOL
Vout
Vin
0
Vtn
5: DC and Transient Response
VIL VIH VDD- VDD
|Vtp|
CMOS VLSI Design 4th Ed.
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Transient Response
 DC analysis tells us Vout if Vin is constant
 Transient analysis tells us Vout(t) if Vin(t) changes
– Requires solving differential equations
 Input is usually considered to be a step or ramp
– From 0 to VDD or vice versa
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
23
Inverter Step Response
 Ex: find step response of inverter driving load cap
Vin (t )  u (t  t0 )VDD
Vin(t)
Vout (t  t0 )  VDD
Vout(t)
Cload
dVout (t )
I dsn (t )

dt
Cload

0


2
b
I dsn (t )  
V

V


DD
2

V (t )
 b VDD  Vt  out 2
 
5: DC and Transient Response
Idsn(t)
Vin(t)
t  t0
Vout  VDD  Vt
 V (t ) V  V  V
 out
out
DD
t

CMOS VLSI Design 4th Ed.
Vout(t)
t0
t
24
Delay Definitions
 tpdr: rising propagation delay
– From input to rising output
crossing VDD/2
 tpdf: falling propagation delay
– From input to falling output
crossing VDD/2
 tpd: average propagation delay
– tpd = (tpdr + tpdf)/2
 tr: rise time
– From output crossing 0.2
VDD to 0.8 VDD
 tf: fall time
– From output crossing 0.8
VDD to 0.2 VDD
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
25
Delay Definitions
 tcdr: rising contamination delay
– From input to rising output crossing VDD/2
 tcdf: falling contamination delay
– From input to falling output crossing VDD/2
 tcd: average contamination delay
– tpd = (tcdr + tcdf)/2
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
26
Simulated Inverter Delay
 Solving differential equations by hand is too hard
 SPICE simulator solves the equations numerically
– Uses more accurate I-V models too!
 But simulations take time to write, may hide insight
2.0
1.5
1.0
(V)
Vin
tpdf = 66ps
tpdr = 83ps
Vout
0.5
0.0
0.0
200p
400p
600p
800p
1n
t(s)
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
27
Delay Estimation Approach 1
VDD
tpHL = CL Vswing/2
Iav
CL
Vout
~
Iav
CL
kn VDD
Vin = V DD
CMOS VLSI Design 4th Ed.
Delay Estimation Approach 2
 We would like to be able to easily estimate delay
– Not as accurate as simulation
– But easier to ask “What if?”
 The step response usually looks like a 1st order RC
response with a decaying exponential.
 Use RC delay models to estimate delay
– C = total capacitance on output node
– Use effective resistance R
– So that tpd = RC
 Characterize transistors by finding their effective R
– Depends on average current as gate switches
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
29
Effective Resistance
 Shockley models have limited value
– Not accurate enough for modern transistors
– Too complicated for much hand analysis
 Simplification: treat transistor as resistor
– Replace Ids(Vds, Vgs) with effective resistance R
• Ids = Vds/R
– R averaged across switching of digital gate
 Too inaccurate to predict current at any given time
– But good enough to predict RC delay
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
30
Delay Estimation Approach 2
VDD
tpHL = f(Ron.CL)
= 0.69 RonCL
Vout
ln(0.5)
Vout
CL
Ron
1
VDD
0.5
0.36
Vin = V DD
RonCL
CMOS VLSI Design 4th Ed.
t
RC Delay Model
 Use equivalent circuits for MOS transistors
– Ideal switch + capacitance and ON resistance
– Unit nMOS has resistance R, capacitance C
– Unit pMOS has resistance 2R, capacitance C
 Capacitance proportional to width
 Resistance inversely proportional to width
d
g
d
k
s
s
kC
R/k
kC
2R/k
g
g
kC
kC
d
k
s
s
5: DC and Transient Response
kC
g
kC
d
CMOS VLSI Design 4th Ed.
32
RC Values
 Capacitance
– C = Cg = Cs = Cd = 2 fF/mm of gate width in 0.6 mm
– Gradually decline to 1 fF/mm in nanometer techs.
 Resistance
– R  6 KW*mm in 0.6 mm process
– Improves with shorter channel lengths
 Unit transistors
– May refer to minimum contacted device (4/2 l)
– Or maybe 1 mm wide device
– Doesn’t matter as long as you are consistent
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
33
Computing Capacitance
 For an inverter driving an identical inverter, the
capacitances in the intermediate node are:
– Cgd12: Since the circuit input is digital, M1 and M2
are either in cut-off or active. Hence, Cgd12 are
only overlap capacitances.
– Cdb1 and Cdb2: These are the diffusion
capacitances. They are voltage variable. Hence
use the approximation Ceq = KeqCj0.
– Cw: Wiring capacitance.
– Cg3 and Cg4: Fanout capacitances
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
34
Computing Capacitance
 Cgd12 is connected between input and intermediate
node.
 Use Miller approximation.
 Use a large signal gain of -1.
 Therefore, the approximate capacitance is given by
2Cov.
 The wiring capacitance will be studied later.
 The gate capacitance is given by:


C fanout  CGSOn  CGDOn W n W n Ln Cox  CGSOp  CGDOp W p W p Lp Cox

5: DC and Transient Response
CMOS VLSI Design 4th Ed.
35
Computing Capacitance
 Actually, there are a few errors in the Cfanout
calculation.
– Miller effect is ignored here.
• Not too bad because Vout of second gate does
not change too much while the calculation is
being done.
– Channel capacitance is assumed to be constant.
• It varies between (2/3)WLCox and WLCox.
 The total error observed is about 10%.
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
36
Computing Capacitance
Term
Expression
Value (fF)
H -> L
Value (fF)
L -> H
Cgd1
2CGDOWn
0.23
0.23
Cgd2
2CGDOWp
0.61
0.61
Cdb1
KeqnADnCJ + KeqswnPDnCJSW
0.66
0.90
Cdb2
KeqpADpCJ + KeqswpPDpCJSW
1.5
1.15
Cg3
(CGDOn + CGSOn)Wn + CoxWnLn
0.76
0.76
Cg4
(CGDOp + CGSOp)Wp + CoxWpLp
2.28
2.28
Cw
From extraction
0.12
0.12
Ctot
Total
6.1
6.0
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
37
Delay Estimation
 Let us use approach 1 first.
V
I C
t
VDD
CV
2
t 
C
I
Iave
Iave 
I Vout  0 I Vout  VDD 2
2
 For approximate results, use the initial value of I

5: DC and Transient Response
CMOS VLSI Design 4th Ed.
38
Delay Estimation
 Then I is given by
W  kp
I   
VDD  VTp
 L p 2


2
 Note that this is the long channel expression. You
can use the velocity saturation or alpha power law
expressions
as well.

5: DC and Transient Response
CMOS VLSI Design 4th Ed.
39
Delay Estimation
 The propagation delay is then,
t pLH 
CLVDD
W 
  kp VDD  VTp
 L p


2
Assume VDD  VTp
t pLH 

5: DC and Transient Response
CL
W 
  kpVDD
 L p
CMOS VLSI Design 4th Ed.
40
Delay Estimation
 Let us use Approach 2.

3 VDD  7
Req 
1  lVDD 

4 IDsat  9
2 
W 
VDsat
IDsat  k VDD  VT VDsat 

L 
2 
t pHL  0.69Reqn CL
t pLH  0.69Reqp CL
t pLH  t pHL
tp 
2
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
41

Delay Estimation
 Ignore l for simpler expressions
t pHL
3
VDD
CLVDD
 0.69 CL
 0.52
W 

VDsat,n 
4
IDsat,n

  knVDsat.n VDD  VTn 
2


 L n
VDsat,n
Assume VDD  VTn 
2
CL
t pHL  0.52
W 
  knVDsat,n
 L n
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
42
Delay Estimation
 Keep C small
 Increase transistor sizes
– Is there a limit?
 Increase supply voltage
– Does this really work?
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
43
Delay as a function of VDD
5.5
5
tp(normalized)
4.5
4
3.5
3
2.5
2
1.5
1
0.8
1
1.2
1.4
1.6
V
1.8
2
2.2
2.4
(V)
DD
CMOS VLSI Design 4th Ed.
Delay Estimation
 Assume a symmetrical inverter (tpLH = tpHL).
 Break up CL into Cint and Cext
– CL = Cint + Cext
– Cint due to driving inverter itself (Cdiff, Cgd)
– Cext due to outside (CL, Cw)
 Then, delay can be written as
t p  0.69Req Cint  Cext 
 Cext 
 Cext 
t p  0.69Req Cint 1
 t p 0 1

C
C


int 
int 
 tp0 is intrinsic delay, self delay, unloaded delay.

5: DC and Transient Response
CMOS VLSI Design 4th Ed.
45
Delay Estimation
 Let us make the W of the transistors in the driving
gate S times bigger to decrease delay.
 Cext 
Req 
t p  0.69 SCint 1

 S 
 SCint 
 Cext 
 t p 0 1

 SCint 
 tp0 is independent of the sizing of the gate and
determined purely by technology and inverter layout.
 Making S infinity gives the minimum delay, but after

a certain point, the improvement is marginal.
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
46
Device Sizing
-11
3.8
x 10
(for fixed load)
3.6
3.4
tp(sec)
3.2
3
Self-loading effect:
Intrinsic capacitances
dominate
2.8
2.6
2.4
2.2
2
2
4
6
8
S
10
12
14
CMOS VLSI Design 4th Ed.
Device Sizing
 So far, we have tried to make tpHL = tpLH.
 Is this optimum?



CL  Cdp1  Cdn1  Cgp 2  Cgn2  Cw
W L
b
W L
p
n


CL  1 b Cdn1  Cgn 2  Cw

Reqp 
0.69
tp 
1 b Cdn1  Cgn 2  Cw Reqn 

2
b



5: DC and Transient Response




CMOS VLSI Design 4th Ed.
48
Device Sizing
 Let us define the ratio of the ‘strengths’ of the PMOS
and the NMOS as
Reqp
r
Reqn
 Then, b can be obtained by finding the derivative of
delay with respect to b.
 t p
0
b
bopt
5: DC and Transient Response


Cw
 r
1 C  C 


dn1
gn 2 
CMOS VLSI Design 4th Ed.
49
NMOS/PMOS ratio
-11
5
x 10
tpLH
tpHL
tp(sec)
4.5
b = Wp/Wn
tp
4
3.5
3
1
1.5
2
2.5
3
3.5
4
4.5
5
b
CMOS VLSI Design 4th Ed.
Inverter Delay Estimate
 Estimate the delay of a fanout-of-1 inverter
2C
R
A
2 Y
2
1
1
2C
2C
2C
2C
Y
R
C
R
C
C
C
C
d = 6RC
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
51
Delay Model Comparison
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
52
Impact of Rise Time on Delay
0.35
tpHL(nsec)
0.3
0.25
0.2
0.15
0
0.2
0.4
0.6
trise (nsec)
0.8
CMOS VLSI Design 4th Ed.
1
Driving Large Loads
 Let us take the case of one unit inverter trying to
drive a large capacitance, CL.
 Let us add one extra inverter as a buffer.
 This inverter is u times the unit inverter.
 CL is x times larger than the capacitance of the unit
inverter.
 What is the size of the buffering inverter?
 Ignore self loading because the external loads are
already large.
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
54
Driving Large Loads
 By writing the expressions and taking derivatives,
 x 
x
t p  ut p 0  t p 0  u  t p 0
 u 
u
dt p
 0, uopt  x
du
t p,opt  2t p 0 x
 Take x = 1000.

 Unbuffered
delay is 1000tp0.
 Buffered delay is approximately 64tp0.
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
55
Driving Large Loads
 If this is still not good enough, let us use a chain of
inverters, each u times larger than the previous one.
t p  Nut p 0 ,
CL  xCin  u N Cin
ln x
ln u
ln x
tp 
ut
ln u p 0
t p
 0  uopt  e  2.7182
u
N
 For x=1000, tp = 19tp0.

 However,
for small u, self loading cannot be ignored.
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
56
Driving Large Loads
 Define a g and an f such that,
g
Cint
Cg
 C 
 f 
ext
t p  t p 0 
1 
1 gC 
 t p 0 
 g 

g 
t p  t p1  t p 2 K  t pN
t p, j
 C

 f j 
g, j 1
 t p 0 
1 gC 
 t p 0 1 g 



g, j 
 Take N-1 partial derivatives. The result is such that
all fj should be identical.

5: DC and Transient Response
CMOS VLSI Design 4th Ed.
57
Driving Large Loads
 Then,
CL N
f N
 F
Cg1
 N F 
t p  Nt p 01

g 

 To find N,
t p
F ln F
N
0g  F 
0 f e
N
N
N
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
1
g
f
58
Driving Large Loads
 This expression is in closed form. It has no explicit
solutions.
 It is solvable only when g = 0. This corresponds to
no self loading and the solution is f = e.
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
59
Driving Large Loads
Optimum f for given process defined by g
f  exp 1  g f 
fopt = 3.6
for g=1
CMOS VLSI Design 4th Ed.
Driving Large Loads
No Self-Loading, g=0
With Self-Loading g=1
u/ln(u)
60.0
40.0
x=10,000
x=1000
20.0
x=100
x=10
0.0
1.0
3.0
5.0
7.0
u
CMOS VLSI Design 4th Ed.
Buffer Design
1
f
tp
1
64
65
2
8
18
64
3
4
15
64
4
2.8
15.3
64
1
8
1
4
16
2.8
8
1
N
64
22.6
CMOS VLSI Design 4th Ed.
Example: 3-input NAND
 Sketch a 3-input NAND with transistor widths chosen to
achieve effective rise and fall resistances equal to a unit
inverter (R).
2
2
2
3
3
3
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
63
3-input NAND Caps
 Annotate the 3-input NAND gate with gate and diffusion
capacitance.
2C
2C
2
2C
5C
2C
2
2C
2
2C
3C
5C
3C
5C
3C
5: DC and Transient Response
2C
2C
2C
3
3
3
CMOS VLSI Design 4th Ed.
9C
3C
3C
3C
3C
64
Elmore Delay
 ON transistors look like resistors
 Pullup or pulldown network modeled as RC ladder
 Elmore delay of RC ladder
t pd 

Ri to sourceCi
nodes i
 R1C1   R1  R2  C2  ...   R1  R2  ...  RN  C N
R1
R2
R3
C1
C2
5: DC and Transient Response
RN
C3
CMOS VLSI Design 4th Ed.
CN
65
Example: 3-input NAND
 Estimate worst-case rising and falling delay of 3-input NAND
driving h identical gates.
2
2
2
Y
3
9C
5hC
n2
3C
3 n1
h copies
3
t pdr  9  5h  RC
5: DC and Transient Response
3C
t pdf   3C   R3    3C   R3  R3    9  5h  C   R3  R3  R3 
 11  5h  RC
CMOS VLSI Design 4th Ed.
66
Delay Components
 Delay has two parts
– Parasitic delay
• 9 or 11 RC
• Independent of load
– Effort delay
• 5h RC
• Proportional to load capacitance
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
67
Contamination Delay
 Best-case (contamination) delay can be substantially less than
propagation delay.
 Ex: If all three inputs fall simultaneously
2
2
2
Y
3
9C
5hC
n2
3C
3 n1
3
3C
tcdr
5: DC and Transient Response
5 
R 
  9  5h  C      3  h  RC
3 
3 
CMOS VLSI Design 4th Ed.
68
Diffusion Capacitance
 We assumed contacted diffusion on every s / d.
 Good layout minimizes diffusion area
 Ex: NAND3 layout shares one diffusion contact
– Reduces output capacitance by 2C
– Merged uncontacted diffusion might help too
2C
2C
Shared
Contacted
Diffusion
Isolated
Contacted
Diffusion
Merged
Uncontacted
Diffusion
2
2
2
3
3
3C 3C 3C
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
3
7C
3C
3C
69
Layout Comparison
 Which layout is better?
VDD
A
VDD
B
Y
GND
5: DC and Transient Response
A
B
Y
GND
CMOS VLSI Design 4th Ed.
70
Delay Calculations
 The above solutions based on Elmore Delay are not
accurate.
 Capacitors discharge in order.
 First, M1 discharges and it is in active mode
C1VDD  VS 
T11 
,
ID 1
VS  VDD  VTn
 Then, M2 starts discharging. Assume first node does
not change much,
C2 VDD VS 

T21 
ID (1,2)
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
71
Delay Calculations
 Once all the nodes are discharged, then the Elmore
formulation above can be applied.
 However, this approach is also not accurate
because
– Internal nodes discharge in order, but the first
node does not remain constant while the second
one is discharging, etc.
– Elmore formula is an upper bound and not exact.
5: DC and Transient Response
CMOS VLSI Design 4th Ed.
72
Scaling Relationships for Long Channel Devices
CMOS VLSI Design 4th Ed.
Transistor Scaling (velocity-saturated devices)
CMOS VLSI Design 4th Ed.