Transcript Document

MICROSYSTEMS LABORATORY
DEPARTMENT OF ELECTRICAL &
COMPUTER ENGINEERING
A CMOS Voltage Adjustable All-Pass Circuit
Robert W. Newcomb
Talk for SWAN 06
December 8, 2006
(Systems Workshop on Adaptive & Networks)
At the Automation and Robotics Research Institute
The University of Texas at Arlington
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With Great Thanks to, and Respect for,
Frank Lewis
And especially for taking the initiative to
Organize SWAN 06
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Main topic of this talk:
The design of a VLSI all-pass CMOS circuit
for variable phase controlled by a voltage .
Possible uses:
An alternate type of phase locked loop
(may have a phase noise advantage)
Phase correction for various purposes.
Outline:
The degree one circuit of Maundy-Aronhime;
Generalization to any degree
Conversion to VLSI transistors; VLSI layout
Spice simulations; MathCad symbolic analysis
At end: Some Microsystems research topics.
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The ideas are based upon the circuit of Maundy & Aronhime.
Their circuit gives
Vout=2*V3-Vin
Using the RC voltage divider V3={(1/sC)/[R+(1/sC)]}Vin
which is
V3={1/[1+sRC]}Vin
gives the degree one all-pass transfer function
Vout/Vin=[1-sRC]/[1+sRC] = T(s)=1/T(-s)
Angle T(jw) = -2*arctan(RCw); |T(jw)|=1
Reference: B. J. Maundy & P. Aronhime, "A Novel First-Order AllPass Filter," International Journal of Electronics, Vol. 89, No. 9,
2002, pp. 739 - 743.
The Maundy - Aronhime Circuit
IDM2=IDM1=>VGSM1=VGSM2=>V3-Vx=Vb-0
IDM4=IDM3=>VGS4=VGS3=>Vin-Vy=Vx-0
IDM6=IDM5=>VGS6=VGS5=>V3-Vo=Vy-0
=> Vo=V3-Vy=V3-[Vin-Vx]=V3-[Vin-(V3-Vb)]
=> Vo=2V3-Vin -Vb
Here Vb is a DC offset;
M4&M3 require Vin offset > 2Vthreshold NMOS
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Generalization to arbitrary rational all-pass
T (s) 
D(-s)
N(s) Vout

 T ()
D(s) V
D(s)
in
withD(s) Hurwit z and monic (1)
set
V
Vout
 T () * (2( 3 )  1)
V
V
in
in
(1) into(2)
V
3  ( 1 ) * ( 1 Vout  1)  [(D(s)D(s)]/2
V
2
T () V
D(s)
in
in
or
V
Ev[D(s)]
z(s)/R
z(s)
3 


V
Ev[D(s)] Od[D(s)] 1  z(s)/R R  z(s)
in
zs  / R  Ev[D(s)]/Od[D(s)]
(2)
where z(s)  R * Ev[D(s)]/Od[D(s)]is a reactancefunctionand, therefore, z(s) is synthesizable as
thedriving pointimpedanceof a lossless1 - port.
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Transistorization for VLSI and with variable R
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Spice run: Phase in degrees
Spice run: Magnitude in DB
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Bias conditions for proper operation
Need to account for offsets due to substrates of M2, M4, M6
Not connected to their sources; adds [(-Vbs)^½-^½] to VTO
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Small Signal Analysis
By replacing each transistor by its pi equivalent, and
Numbering x=4, y=5, ground=6, the indefinite Y matrix
is obtained. Deleting the 6th row and column yields the
nodal admittance matrix.
0
 s  Cg  gor


0
s  Cg  gm6  go5  go6 

Y11s
( )  
g or
s  Cg s 



Y 21s
( ) 
0
0


 s  Cg s  g m4 s  Cg d 
gor
0
s  Cgs




s

Cgs

gm6
0

s

Cgd

gm5


Y12s
( )  
s  Cg s
0
 s  C3  g or



Y 22s
( )   s  Cg s  g m2 s  ( 2 Cg)  g m2  g o2  g o1
s  Cg d

 *
0
s  Cg d  g m3
s  ( 2 Cg)  g m4  g o4  g o3

Form the 2-port Y(s)=Y11-Y12*Z22*Y21 where Z22=Y22^-1
From which: T(s)=-Y(s)[2,1]/Y(s)[2,2]
Display by float 4 to 4 digits and then solve, for the poles and
zeros at different resistor control voltages, Vr.
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Using MathCad symbolic analysis, by eliminating
Internal nodes (3,4,5) the transfer function is obtained
At Vr=1;
3
2
4
.3 40 8e59s  .4 60 1e71s  .4 24 5e82s  .1 93 6e8 9 .5 11 3e48s
T1( s )   .1 00 0e-1

4
3
2
.3 33 6e47s  .1 43 6e59s  .1 55 2e70s  .4 13 6e80s  .1 89 2e8 7
 2 80 22 40 17 9 03 .14 24 78
 65
 2 81 53 38 8 18 97 .68 2 6821 9





1
10
01
98
83
2
11
.21
68
93
2
6

9 51 30 92 7 32 7.5 39 1 1532 6
T1p ol es  

 4 02 07 15 91 2 3.7 03 93 54
 3 1 T1zeros   
4 56 04 34 .1 83 15 66 0 3204 4
 4 57 52 53 .54 3 40 72 94 59
 02
 3 10 00 66 2 07 83 .99 7 7647 1




At Vr=2;
3
2
4
.3 40 7e59s  .4 60 1e71s  .4 24 5e82s  .2 39 4e8 8 .5 11 3e48s
T2( s )   .1 00 0e-1

4
3
2
.3 33 6e47s  .1 43 6e59s  .1 55 2e70s  .4 13 6e80s  .2 34 3e8 6
 8 31 19 04 81 62 80 7 65 27
 55 .


3 10 70 02 11 45 53 5 85 82

 93 .
P o les 
 1 28 49 29 99 96 21 0 57 64
 79 .
 2 26 73 89 .34 05 60 6 99 68
 97


 8 44 95 39 71 2 45 19 94 91
 7 4.


2 55 77 25 63 4 31 87 38 95

 9 9.
Zero s  
 2 25 23 88 .72 0 57 77 60 78 7 1
 7 76 65 06 49 6 78 02 87 633 2.


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Mathcad plots from symbolic transfer function
0
20
40
60
P hase1( w)
P hase2( w)
80
100
120
140
160
180
200
100
10
1 10
3
1 10
1 10
4
5
1 10
6
1 10
7
w
A1( w )
A2( w )
1
0.1
100
1 10
3
1 10
1 10
4
5
w
1 10
6
1 10
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VLSI Layout for 1.2U AMI fabrication
Vdd
Vr
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6 main transistors
10ux10u, cap 38ux32u
Out
In
Vb
Gnd
Other research topics of Microsystems Laboratory:
1. Use of ABR (=Acoustic Brain-Stem Response) for
characterizing hearing loss and creation of hearing aids.
Possible use for control of Parkinsons' disease.
2. Use of Beeler-Reuter heart models for VLSI mimic
of heart electrical control for effect of drugs on
arrythmias.
3. Spice models for flexible transistor circuit design.
4. Spice models of DNA electrical characterization
and use of braid group models of DNA type structures.
5. Use of nano sized Y-junctions for room temperature
nano-computers based upon electron swarms.
6. Neural networks using single electron quantum dots.
7. VLSI realization of Prof. Roa’s neural simulink model
incorporating Ca channels.
8. Wireless data collection for on patient sensors
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