Transcript CSCE 612: VLSI System Design

CSCE 612: VLSI System Design
Instructor: Jason D. Bakos
Elements
VLSI System Design 2
Semiconductors
•
Silicon is a group IV element (4 valence electrons, shells: 2, 8, 18, …)
– Forms covalent bonds with four neighbor atoms (cubic crystal lattice)
– Si is a poor conductor, but conduction characteristics may be altered
– Add impurities/dopants (replaces silicon atom in lattice):
•
•
Makes a better conductor
Group V element (phosphorus/arsenic) => 5 valence electrons
–
•
Leaves an electron free => n-type semiconductor (electrons, negative carriers)
Group III element (boron) => 3 valence electrons
–
Borrows an electron from neighbor => p-type semiconductor (holes, positive carriers)
+P-N junction
- +
+++ --- +
+++ --- +
+drift
forward bias
reverse bias
VLSI System Design 3
MOSFETs
• Diodes not very useful for building logic
• Metal-oxide-semiconductor structures built onto substrate
– Diffusion: Inject dopants into substrate
– Oxidation: Form layer of SiO2 (glass)
– Deposition and etching: Add aluminum/copper wires
negative
charge (rel.
to body)
(GND)
positive charge
(Vdd)
PFET/NFET
current
body/bulk
GROUND
---
+++
---
+++
channel
shorter length,
faster transistor
(dist. for
electrons)
PMOS/PFET
current
body/bulk
(S/D to body is
reverse-biased)
HIGH
VLSI System Design 4
FETs as Switches
• NFETs and PFETs can act as switches
CMOS
logic
bulk
node not
shown
“and structure”
“or structure”
pull-up
OFF
pull-up
ON
pull-down
OFF
Z
(floating)
1
pull-down
ON
0
smokin’!
CMOS: assuming PU and
PN network are perfect
switches and switch
simultanously, no current flow
and no power consumption!
VLSI System Design 5
Logic Gates
•
•
•
•
NMOS devices (positive logic) form pulldown network
PMOS devices (negative logic) form pullup network
Implication: CMOS transistor-level logic
gates implement functions where may
the inputs are inverted (inverting gates)
Add inverter at inputs/outputs to create
non-inverting gate
NAND2
Y  A B
Y  A B
inv
YA
NOR2
NAND3
Y  A B
Y  A B
DeMorgan’s Law
A B  A B
VLSI System Design 6
Compound Gates
•
Combine parallel and series structures to form
compound gates

 
Y  A B C  D
Example:
–
Use DeMorgan’s law to determine complement (pulldown network):
Y   A  B   C   D
C
A
  
Y  A  B  C  D
Y   A  B   C  D
Y  A B C  D
–
B
D
Y
A
C
B
D
VLSI System Design 7
Pass Transistors/Transmission Gates
• NMOS passes strong 0 (pull-down)
• PMOS passes strong 1 (pull-up)
Pass transistor:
Transmission gate:
VLSI System Design 8
Tristates
VLSI System Design 9
Multiplexer
Transmission gate multiplexer
Inverting multiplexer
VLSI System Design 10
Multiplexer
4-input multiplexer
VLSI System Design 11
Latches
Positive level-sensitive latch
VLSI System Design 12
Latches
Positive edge-sensitive latch
VLSI System Design 13
IC Fabrication
• Inverter cross-section
field oxide
VLSI System Design 14
IC Fabrication
• Inverter cross-section with well and substrate contacts
(ohmic contact)
VLSI System Design 15
IC Fabrication
•
Chips are fabricated using set of masks
– Photolithography
•
Inverter uses 6 layers:
– n-well, poly, n+ diffusion, p+ diffusion,
contact, metal
VLSI System Design 16
IC Fabrication
Furnace used to oxidize (900-1200 C)
Mask exposes photoresist to light,
allowing removal
HF acid etch
piranha acid etch
diffusion (gas) or ion implantation
(electric field)
HF acid etch
VLSI System Design 17
IC Fabrication
Heavy doped poly is grown with gas in
furnace (chemical vapor deposition)
Masked used to pattern poly
VLSI System Design 18
IC Fabrication
Metal is sputtered
(with vapor) and
plasma etched from
mask
VLSI System Design 19
Layout Design Rules
•
Design rules define ranges for features
– Examples:
•
•
•
min. wire widths to avoid breaks
min. spacings to avoid shorts
minimum overlaps to ensure complete overlaps
– Measured in microns
– Required for resolution/tolerances of masks
•
Fabrication processes defined by minimum channel width
– Also minimum width of poly traces
– Defines “how fast” a fabrication process is
•
Lambda-based (scalable CMOS) design rules define scalable rules based
on l (which is half of the minimum channel length)
– classes of MOSIS SCMOS rules: SUBMICRON, DEEP SUBMICRON
VLSI System Design 20
Layout Design Rules
VLSI System Design 21
Layout Design Rules
• Transistor dimensions are in W/L ratio
– NFETs are usually twice the width
– PFETs are usually twice the width of NFETs
• Holes move more slowly than electrons (must be wider to deliver same
current)
VLSI System Design 22
Layout
3-input NAND
VLSI System Design 23
Design Flow
• Design flow is a sequence of steps for design and
verification
• In this course:
–
–
–
–
–
–
Describe behaviors with VHDL/Verilog code
Simulate behavioral designs
Synthesize behaviors into cell-level netlists
Simulate netlists with cell-delay models
Place-and-route netlists into a physical design
Simulate netlists with cell-delay models and wire-delay models
• Need to define a cell library:
– Function
– Electrical characteristics of each cell
– Layout
VLSI System Design 24
Cell Library (Snap Together)
Layout
VLSI System Design 25