Transcript Design_TWG_pres_SF_7

ITRS/ Design TWG Update 2000
System on Chip, Design Productivity, Low Power, Deep
Submicron Design requirements, Future role of Design
TWG
Proposal
ITRS 2000 Update
Contact: Werner Weber, +49 89 48470, [email protected]
1
ITRS 2000 Update Work In
Scenario for SoC Productivity
Year
Node
% Area New Logic
% Area Reused Logic
% Area Memory
Transistor Logic Density
(Mtrans/cm2)
New Logic Productivity
(Mtrans/PY)
Reused Logic Productivity
(Mtrans/PY)
Target Design Resource (PY)
1999
2002
2005
2008
2011
2014
180 nm 130 nm 100 nm 70 nm 50 nm 35 nm
64%
16%
20%
32%
16%
52%
16%
13%
71%
8%
9%
83%
4%
6%
90%
2%
4%
94%
20
54
133
328
811
2000
1,4
2,1
2,9
4,2
6,0
8,6
2,9
10,0
4,1
10,5
5,9
10,1
8,4
9,9
12,0
9,7
17,1
9,6
2
ITRS 2000 Update Work In
Scenario: major increase in memory content
100%
80%
60%
% Area Memory
40%
% Area Reused
Logic
20%
% Area New Logic
19
99
20
02
20
05
20
08
20
11
20
14
0%
3
ITRS 2000 Update Work In
Comments:
I hate to be a seagull (fly in, poop, fly away), but even though I'm not active in this spin, I need to know
how the group arrived at the data used in the SoC slide you sent.
Frankly, I don't buy it, and I don't think my company would, either! Again and again, everyone thinks that
memory is the answer to all that "empty space" on silicon, but the actual numbers we see never align with
that -- there's plenty of logic needs, and memory is more efficient when not encumbered by a logic
process (and vice-versa). Our ASIC group sees a lot of SRAM, but it's never more than about half the
chip, worst-case. All the new design wins we are getting indicates its the tightly integrated, fast logic that
sells the high-end and medium-end volumes. Sure, on-chip memory will grow by 10x and more -- but
94% of the area? Reused logic <10% of the chip? C'mon!!!
Please explain what I'm missing here -- this doesn't sound consistent to me.
I was wondering the same thing. But then I wonder if they might have in mind that with the faster
technologies that the new transistors will bring perhaps more functionality can be put in software vs.
hardware and still be able to meet "real time" needs.
I feel that we should remember the premises and the motivations for that exercise: "what should we do to
increase the design productivity, and keep the size of the design team constant (10 man-year)?"
Is this exercise useful, I don't know.
The solution found by the STRJ consists in putting less logic (more memories) and do more reuse.
Anyway 10% of logic in year 2011 gives a significantly high number of gates! So, the approach is not
completely crazy, but I agree that it's hard to propose accurate numbers on that topic.
Conclusion: no final result yet
4
ITRS 2000 Update Work In
Low Power
SOC Low Power
Total Power Trend with
No Low Power Solution
Total Power Trend with
Low Power Solution Scenario
to keep 3W
100
100
10
10
1
1999
2002
2005
2011
volatage
frequency
1
1999
2002
2005
2011
0.1
0.1
0.01
size
process
voltage
frequency
total
ITRS 2000 Update Work In
size
process
total
5
ITRS, meeting in Leuven
DSM
An overall DSM requirements table
Base data/Condition
(table 2-1-4-1) DSM requirements
unit
1999
2002
2005
nm
180
130
100
50
Nominal Ion [25c,NMOS,low power]
uA/um
490
490
490
490
Nominal Ion [25c,PMOS,low power]
uA/um
230
230
230
230
ITRS99 Table28
V
1.5
1.2
0.9
0.6
STRJ-WG1/LP-SWG
Frequency
MHz
150
400
1000
2000
STRJ-WG1/LP-SWG
Die size
cm□
1
1
1
1
STRJ-WG1/LP-SWG
2
2.1
1.7
2.1
STRJ -WG4
Metal effective resistivity
μΩcm
2.2
2.2
2.2
<1.8
STRJ -WG4
Maximum metal current
mA
2.16
1.56
1.2
0.6
STRJ -WG4
mm
1.08
0.78
0.60
0.30
mm
2.70
0.21
0.00
0.00
mm
10
10
10
10
mm
289
67
12
2
Technology node
Voltage
Metal height/width aspect
2011
Reference
ITRS99 Table28
Signal Integrity
DSM Category
Crosstalk noise Required parallel interconnect maximum allowable length
which considers parastic capacitence effect
Required
Estimated parallel interconnect maximum allowable length
which considers parastic capacitence effect
Estimated
RC delay
Required interconnect maximum allowable length which
considers resistence
Required
Estimated interconnect maximum allowable length which
considers resistence
Estimated
Inductance
Interconnect Inductance Effect
EMI
Allowed
Man
ufac
ture
Reliability
Estimated
IR drop
Required
Estimated
ElectroMigration
OPE
(*a) Next Page
(*b) Next
CP1 (*1) CP2 (*2)
Allowable EMI by FCCclassB (at a distance of 3.0m )
uV/m
150
200
500
500
Estimated EMI by a chip (observation point =3.0m)
uV/m
11
22
43
43
Required maximum allowable number of FF which is
driven by power line without failure due to IR Drop.
Estimated maximum allowable number of FF which is
driven by power line without failure due to IR Drop.
20
20
20
20
34
21
10
5
Number of Power Pads (High Performance)
342
472
800
1,066
Number of Power Pads (Battery/Hand-Held)
6
9
16
16
Number of Power Pads (Target of LP-SWG)
2
2
3
4
CP
CP
Optical Proximity Correction
CP1(1st Crisis Point): Interconnect effects becomes critical in high speed blocks(1GHz).
CP2(2nd Crisis Point): Interconnect effects becomes major delay in high speed blocks(2GHz).
ITRS 2000 Update Work In
See
tab.2-1-4-2
Page
See
tab.2-1-4-3
(*c) Next Page
(*d) Next
See
tab.2-1-4-4
Page
See
tab.2-1-4-5
See
tab.2-1-4-6
6
ITRS, meeting in Leuven
Proposal or Concern on ITRS2000 and beyond
- Definition of scope for “Design”
・ Does it mainly address hardware implementation
technologies ?
・ It needs to include system integration, software
technologies and embedded blocks (RF, analog,
MEMS,)
- Need “Design technology nodes” in addition
design technology turning-points, for example
・ IP design
・ DSM related technologies
・ Power supply scheme
7
ITRS 2000 Update Work In
Proposal or Concern on ITRS2000 and beyond
(cont'd)
Results of recent discussions:
Design TWG plans for a much more active role in the
field of mixed signal design.
8
ITRS 2000 Update Work In
The World of the Living
Roadmap
Firewall
Technology
Models
The
Internet
Proprietary
Models
Sematech, GSRC
University
Researchers
Richard Newton
ITRS 2000 Update Work In
“The Golden Copy”
9
Questions addressed in consultations with
other TWGs
Meeting with PIDs:
• Agreement to work together on numbers for power
saving, gate leakage spec, benchmark circuits (analog
and matching)
Meeting with interconnect TWG:
• Agreement to cooperate on task force on parameter
improvements for contact resistances (tungsten?),
metal resistivities (copper?), and intermetal dielectric
constants
10
ITRS 2000 Update Work In
Questions addressed in consultations with
other TWGs (cont'd)
Meeting with Test TWG, Assembly and Packaging:
• Design will review the frequency numbers in the
tables based on inputs from Japanese roadmap
11
ITRS 2000 Update Work In