Transcript Design-ITWG-2000Dec12

Design ITWG Mtg.
~ Toward the ITRS 2001
Design Chapter and SoC Chapter ~
STRJ-WG1
Dec 2000
December 12,2000 - 1
STRJ-WG1
Meeting agenda
◆ Taiwan ITRS Meeting Report
- Generic info on ITRS1999 update
- Important direction for ITRS2001
- etc.
◆ Analog Roadmap presentation from Europe
- sketch a new analog roadmap
Ralf Brederlon will present
◆ Discussion and Planning on ITRS2001
- “SoC Chapter” --- “System Drivers” proposal from US
- “Design Chapter” --- New contents to be added, etc.
◆ Misc.
- International cooperation, 2001 meeting schedule, and etc.
December 12,2000 - 2
STRJ-WG1
(ITRS 1999 update - Design Chapter)
Scenario for SoC Design Productivity
Design productivity and the productivity gap have long been cited in the ITRS and
its predecessors and in other roadmaps as indications of how productivity will have
to increase to make use of the ever-growing number of circuits available on a chip.
This table expands on that notion and extends it, going a step farther and
suggesting possible ways in which the increased density made available along the
Moore’s law path will be used by designers. We point out that this is not the only
scenario for design, but is an attempt at a reasonable path in a particular case.
The assumptions are that for a short time-to-product, small design team effort of a
single-chip system, the team size and time-to market cannot grow much. A 10person team, one-year design cycle is assumed. Design productivity (transistors
per designer per month) for new logic is assumed to increase at 30% per year, a
number greater than the design productivity number of the “productivity gap” chart
but in line with recent figures. Reuse of old designs is not assumed to be free, but
is estimated at one-half the effort of new design, with productivity increasing at the
same rate. Chip size is assumed to be one square centimeter, but with memory
occupying the part of the chip not occupied by the feasible design effort.
It is important to note that in the result, the absolute number of logic transistors
increases greatly, despite the fact that the portion of the chip occupied by new and
reused logic decreases to less than 10% of the available area.
December 12,2000 - 3
STRJ-WG1
(ITRS 1999 update - Design Chapter)
Scenario for SoC Design Productivity
Year
Node
1999
2002
2005
2008
2011
2014
180 nm 130 nm 100 nm 70 nm 50 nm 35 nm
% Area New Logic
% Area Reused Logic
% Area Memory
Transistor Logic Density
(Mtrans/cm2)
New Logic Productivity
(Mtrans/PY)
Reused Logic Productivity
(Mtrans/PY)
Target Design Resource (PY)
64%
16%
20%
32%
16%
52%
16%
13%
71%
8%
9%
83%
4%
6%
90%
2%
4%
94%
20
54
133
328
811
2000
1.4
2.1
2.9
4.2
6.0
8.6
2.9
10.0
4.1
10.5
5.9
10.1
8.4
9.9
12.0
9.7
17.1
9.6
100%
% Area Memory
80%
60%
40%
% Area Reused
Logic
20%
% Area New Logic
December 12,2000 - 4
14
20
11
20
08
20
05
02
20
20
19
99
0%
STRJ-WG1
Is there any important info from
Taiwan ITRS Meeting ?
Memo
December 12,2000 - 5
STRJ-WG1
◆ Analog Roadmap presentation from Europe
December 12,2000 - 6
STRJ-WG1
◆ Discussion and Planning on ITRS2001
December 12,2000 - 7
STRJ-WG1
◇ SoC Chapter in ITRS 1999
〇 What is a System-On-a-Chip?
- Main Emphasis - Cost-Based Designs
- Programmable versus Hard-Wired
〇 Process Requirements for Advanced Technologies
〇 Packaging Considerations
- System-On-a-Chip Packaging
- RF and Mixed-Signal Packaging
- Multi-Chip Packages, Multi-Chip Modules, and System-In-a-Packaging
〇 Test for SoC
(Tables) Table 8 Major Characteristics and Emphasis of SoC Classifications
Table 9 Example of Circuit Fabrics
Table 10 Example Applications of Programmable and Nonprogrammable SoCs
Table 11 Added Process Complexity for SoC Technologies
Table 12a SoC Test Technology Requirements - Near Term
Table 12b SoC Test Technology Requirements - Long Term
December 12,2000 - 8
STRJ-WG1
◇ SoC/System Drivers Chapter in ITRS 2001
◇ Design Chapter in ITRS 2001
( Just a Strawman ! )
〇 Defining the major system types
(e.g., high-volume/low volume MPU, ASIC, and SOC)
〇 Features and profiles for each typical type “SoC”
〇 Comprehensive analysis for required technologies
for each type of “SoC”, if those are specific to types
〇 Entire design methodology Roadmap from System level
to Mask making
〇 High-lighting IP reuse methodology Roadmap
〇 Design Productivity scenario for each typical type “SoC”
December 12,2000 - 9
STRJ-WG1
◇ SoC/System Drivers Chapter in ITRS 2001
◇ Design Chapter in ITRS 2001
( Just a Strawman ! )
〇 Updates from ITRS 1999 Design Chapter
(e.g., Design Complexity, Design Difficult Challenges )
〇 Analog/RF roadmap tables with descriptions
〇 Low Power roadmap table with description
〇 Detail analysis on some most difficult issues in design
(e.g., Analog macro design, 3D extraction, Power, Noise,
Signal Integrity, System simulation, Formal Checking,
Chip Test, Diagnostics )
〇 Need more Roadmap tables !
December 12,2000 - 10
STRJ-WG1
◇ What STRJ/WG1 Plans for STRJ2001
〇 In STRJ1999 We focused on
- Design Productivity Roadmap
- Low Power Roadmap
- Deep Sub-micron technology requirements Roadmap
〇 Candidates for STRJ 2001
( Now, under discussions )
- System level design (including S/W design) Roadmap
- Revise Design Productivity Roadmap table
- Investigate “Jisso” related technology requirements and
make some Roadmap
- Deepen Joint activities with other TWGs
December 12,2000 - 11
STRJ-WG1
◆
Misc.
- Another meeting in addition to 3/Year ITRS ITWG Mtg.
- Participation from Taiwan and Korea
- Any good idea to share task among US, Europe
and Japan
- Need Design ITWG chairman
- Cross cut items (eg. Interconnect, Transistor)
- etc.
December 12,2000 - 12
STRJ-WG1