Transcript CAD_for_Codesign

Computer-Aided Co-design
Methods and Tools
Part of
HW/SW Codesign of Embedded
Systems Course (CE 40-226)
Winter-Spring 2001
Codesign of Embedded Systems
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Today programme
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Introduction to HW/SW Codesign
 Computer-aided codesign methods and
tools
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Motivations
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System designer goals
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Satisfy system-level specifications in a
short time
Maximize system value
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Performance, power consumption, applicability
to various user demands
Minimize cost
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Number of HW parts, size of silicon die, cost of
SW development
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Motivations (cont’d)
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CAD tools are useful, because
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Require formal system-level specification =>
structured design methodology
Facilitate HW and SW reuse
Support analysis and validation tools
Facilitate design-space exploration
Overall objective in codesign tool R&D
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Provide IDE for concurrent specification,
validation, and synthesis of both HW and SW
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Modeling
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Model of computation vs. HW/SW language
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Computation model:
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Languages:
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Has an underlying mathematical structure: FSM, Petri net
Some are means of expressing a computation model
Some don’t have a formal semantics
Functional modeling of digital systems
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Normally C or C++, to check generic properties
and derive some measure of performance & cost
Too general. Do not capture all necessary
specifications of HW component
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Modeling (cont’d)
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Some specification models
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“FSM or interconnection of FSMs” Model
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Partial-orders of tasks
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Graphical representation: Statecharts
Textual languages: SDL, Esterel
HW components: Verilog / VHDL
Synchronous data-flows: Silage, DFL
A perfect language for system is idealistic
Heterogeneity of system components
 Conflicting interests of CAD developers and users
 Lack of a formalism to capture well all features
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Validation
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Validation vs. verification
Approaches to validation
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Formal verification
Simulation (co-simulation)
Emulation
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Validation (cont’d)
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Simulation
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cannot ensure correctness, but still useful
Heterogeneity
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Weakly heterogeneous
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Lumped, GP computing systems. Simple control systems
Can be simulated by extending HDL simulators
Strongly heteroneous
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Cellular phones, avionics
Require specialized simulation environments
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Validation (cont’d)
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Simulator features for weakly
heterogeneous systems
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Adequate timing accuracy
Fast execution
Visibility of internal registers for debugging
Strategy 1: Use HDL simulator + HDL
models for processor and ASICs
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Long HW simulation time for each
instruction: accuracy vs. speed tradeoff
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Validation (cont’d)
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Strategy 2: avoid processor HDL model
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Use HW/SW comm. Protocol
SW is compiled and communicates with the
HDL simulator which models ASIC
HDL simulator is bottle-neck
Internal registers not visible
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Validation (cont’d)
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Strategy 3: Emulate HW on a reconfigurable platform
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Automatic partitioning tools to minimize
system-simulation time have been
developed
Visibility of internal states is limited =>
probable slow debugging
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Validation (cont’d)
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Simulation of strongly heterogeneous
and distributed systems
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Specialized simulators: Ptolemy
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Extesible, OO kernel
Supports several computation models
Models are not implemented in simulation
kernel, but in domains that can interact without
knowing their semantics
Some developed domains: data-flow, discreteevent. More domains are user-insertable.
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Synthesis
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What’s Synthesis/Co-Synthesis
System-level Partitioning
Hardware synthesis
Software synthesis and retargetable
compilation
Interface synthesis
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Synthesis (cont’d)
HW: HDL
(Behavioral,
DataFlow, Structural),
Schematic
Specification
Co-Synthesis
SW: Algorithm,
Textual/Graphical
representation
Synthesis
RTL, Gate level,
Transistors,
Layout
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Detailed Representation
of Implementation
Codesign of Embedded Systems
Executable or
Compilable
code: The
program(s), OS
routines 14
Synthesis (cont’d)
Traditional System Design Process
Tasks
SW design
SW test
System
design
PCB test
ASIC design
Fabrication
Test
Time
Copyright J. Madsen,
some modifications applied
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Synthesis (cont’d)
Co-Design Process
Tasks
SW design
SW test
System
design
Shared Design
ASIC design
Fabrication
PCB test
Test
Time
System-Level Partitioning
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Synthesis (cont’d)
Some special cases
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Synthesis of ISPs
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HLS techniques are applicable to high-level models
of processors
Many high-level decisions are not automatic yet
 Example: Pipeline organization, Datapath design
 Reason:
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Few new ISPs compared to ASICs
Performance is very sensitive
High production-volume recovers high design costs
HLS is, however, used for control functions
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Synthesis (cont’d)
Some special cases
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Design of compilers
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Corresponds to the processor architecture
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Compilers are co-designed with processors
Automated tools for synthesis of pipeline control
unit + compiler
Synthesis of lumped embedded systems
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Natural evolution of HLS
Uniform specification + manually or
automatically partitioning into
HW+SW+interface
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Synthesis (cont’d)
System-Level Partitioning
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One extreme: Full HW solution
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Other extreme: Full SW solution
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High performance due to Parallelism
High cost and long time of ASIC fabrication
High-performance, low-cost processors
Operation serialization
Lack of support for specific tasks
Best solution is a mix of HW and SW
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Synthesis (cont’d)
System-Level Partitioning
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Major approaches to Partitioning
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Co-synthesis of dedicated co-processors for
SW execution acceleration
Migration of non-critical functions to SW
Complementary objectives
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Maximize performance
Minimize system cost, subject to required
performance
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Synthesis (cont’d)
System-Level Partitioning
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Coprocessor approach:
COSYMA tool suite
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System model in C*
SW implementation of
system readily available
Uses CDFG
Identifies performance
bottlenecks
Migrates bottleneck to
corresponding ASIC
Three times faster execution
of an algorithm in HDTV
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Migration to SW approach:
VULCAN tool suite
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System model in HardwareC
System is HW synthesizable
using Olympus
Uses CDFG
Partitions CDFG into SW
threads and HW circuits
Automatically generates
units to interface processor
to the ASIC
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Synthesis (cont’d)
System-Level Partitioning
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Problems in Partitioning
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Quality of partition depends on performance/cost
estimators
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Estimators base on abstract system representation
(CDFG)
Estimators need to be fast
A coarse-grained partition may be of more interest
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Module/Unit level partition instead of operation-level
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Less degree of freedom
Designers’ expertise can be more easily exploited by
allowing macroscopic choices
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Synthesis (cont’d)
HW synthesis
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Mostly based on Graph-theoretic approaches
and algorithms
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(To be presented as an extra class)
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Synthesis (cont’d)
SW synthesis
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SW Synthesis and Retargetable Compilation
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SW synthesis  Compilation
Maybe preceded by automatic SW generation steps
Compilation specialties in embedded systems
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Code is compiled once=> compilation time not important,
maximum optimization is desired
RT constraints=>code must be tight and fast => assembly
Embedded systems often use ASIPs=>unordinary
architectures=>hard to compilers
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Synthesis (cont’d)
SW synthesis
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Retargetable Compilers
 Developing a new compiler for each new
ASIP is unreasonable=>retargetable
compilers
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Classification according to retargeting time
 Portable compiler
 Compiler-compiler
 Machine-independent compiler
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Synthesis (cont’d)
SW synthesis
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Compiler components
Source-code-dependant
Front-end
Code-generation/optimization
intermediate stage
Code-generation
back-end
instruction
selection
Winter-Spring 2001
register
allocation
Codesign of Embedded Systems
instruction
scheduling
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Synthesis (cont’d)
SW synthesis
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Other topics in retargetable compilation
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Micro-programmed ASIPs
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Compacting the micro-program
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Determine ILP (Instruction-Level Parallelism)
Encoding of each word
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Synthesis (cont’d)
Interface synthesis
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Interface Synthesis
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Generation of SW routines and/or HW circuits to
interface processor and ASIC to a communication
channel operating under a given protocol (e.g. PCI,
VME)
Several standards available & system-level model
should avoid specifying details of comm.
mechanism
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An approach: model comm. protocol with a language
(Promela) and derive C++ routines and gate-level HW out
of it
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Synthesis (cont’d)
Interface synthesis
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Interface Synthesis (cont’d)
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Specific problems arise from:
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Partitioning a system into interacting HW and SW
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Interfacing processors to peripherals (sensors, actuators)
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Communication and synchronization
CHINOOK: automatic (processor port allocation, deciding
to implement device drivers in HW or SW)
Scheduling the processor communication
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Complicated under RT constraints
Complicated under data-dependant delays
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Summary
System
Specification
Verification
Co-Synthesis
Partitioning
Verification
HW Parameter
Estimation
SW Parameter
Estimation
HW
Synthesis
SW
Synthesis
ASIC
OS
EXE Code
System
Integration
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Verification
Codesign of Embedded Systems
Verification
Final Verification
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Summary (cont’d)
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CAD Tools are essential to progress in electrical
system design
Design of digital components of systems benefit from
HW/SW Codesign
At present, Codesign CAD support is still weak
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Co-simulators commercially available
Others (co-synthesis, verification, IDEs, etc) growing up
Impact of CAD tools on system-level design will be
more profound than their impact on IC design
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What we learned today
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CAD tools are essential to success in this field
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They must support Modeling (specification),
Validation, and Synthesis in a single integrated
environment
Major constituents of codesign
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Modeling (Specification)
Validation (Verification)
Synthesis (Co-synthesis)
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Winter-Spring 2001
System-level partitioning
HW synthesis
SW synthesis
Interface synthesis
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Complementary notes
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Postponed Verilog Short Course
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Instructor:
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Farshid Soheili, Emad Semicon. Co.
First session
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Saturday: Esfand 13th
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“CE-202” room, 15 o’clock
Take the first chapter of DeMicheli’s
book from “Publications Room”
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Complementary notes (cont’d)
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Optional paper presentation
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Any subtopic from last and today
programme:
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Computer-Aided Codesign Methods and Tools
Project
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Today is date to choose and announce your
partner for the final project
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