ForJohn_SlidesTestSystem_jpt_7Aug13
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Transcript ForJohn_SlidesTestSystem_jpt_7Aug13
Test system with Hybrid (1)
- Small vacuum
pump holding hybrid
flat on panel (which
it is ‘strong enough’
to do)
- Since picture was
taken have added
stronger cooling fan
(12cm, 12V, 0.4A)
above hybrid. Simple
handheld IR
temperature
measurement tool
shows: ~36C at chip
- Power supplies
CPX200 for hybrid,
HSIO (12V) and
cooling fans.
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Test system with Hybrid (2)
Test-Hybrid from
Liverpool with 20
chips (‘Chip6 not
working’ sticker)
One hybrid on
panel, panel
screwed onto
bonding plate.
Powered 3.3V DC
(actually should
be 2.5V, but then
don’t get data
transmission.
Same behaviour
with or without
LVDS Adaptor
board.) Current
drawn: 4.4-4.8A
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Wire-boding hybrid to panel
Hybrid on panel from
Liverpool initially
didn’t draw any
current.
Microcope inspection:
No wires between
hybrid and panel.
-> Simon added those
using our Hesse wirebonder.
Top image: Power
input side. Bottom
pads are on hybrid,
top side is panel.
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Bottom Image:
Data-lines (LVDS)
side.
Bottom pads are
on hybrid, top
side is panel.
Some wire-pads
not to be
connected.
Our connections
are correct
(Simon send
picture to Ashley
in Liverpool to
verify)
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Hybrid power-up: ‘st_nmask’ test
-SCTDAQ s/w setup
modified to run in
‘Hybrid’ mode (before:
Single-Chip testboard
mode)
Thanks again to Bruce
and Peter at RAL.
-Running:
.x NoBCCSetup.cpp
-‘st_nmask’ shows: All
20 chips responding
-> Now can start
running more serious
tests...
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First Hybrid test: ‘StrobeDelay0.4’
Left: Screenshot of ‘ScanData’ histo
window of ‘StrobeDelay 0.4’ test
(Faulty ‘Chip6’ showing ?)
Below: $SCTVAR/ps/ABCNHybrid_F02_
StrobeDelayPlot_20130801_114240.ps
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Glue Tests (1)
Image: Glass ASICs on hybrid
test cured overnight.
Top hybrid: Earlier attempt,
Middle hybrid: latest attempt.
Visible improvement
“There is one die (Top, 5th
fromright) that is on the limit but
it would pass, there is no glue
touching the bond pads.
In the image there is an example
at the top of a previous glass
ASIC test that had too much glue
that spread onto the bond pads,
this makes a good comparison.”
Next: One more Glass ASIC test,
then use real ASICs.
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Glue Tests (2)
… the same image after some Photo Editor treatment …
Top hybrid: Earlier gluing attempts, bottom hybrid: latest attempt.
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Back-up Slides
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Single-Chip Testboard (1)
-Test mode:
“CaptureBurst”. One of
ABC-N chip’s
‘self-test’ modes.
-Left side of signal
pattern: Data header.
Right side: area should
be very close to full
height. Indicating ABC-N
internal analogue voltage
circuitry is active (this
required jumper switch)
-Location of entries
indicates clocks are ok
(HSIO at same frequency
as ABC-N chip)
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Single-Chip Testboard (2)
-Histogram:
Test mode:
‘st_nmask’:
Black triangle means
‘Good’. One triangle
per chip.
-Scope screenshot:
‘DelayScan’.
LEMO output from
HSIO (after
transformation
LVDS->TTL inside
Xilinx FPGA, ie ‘by
definition nice
signals’)
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Test system with Hybrid (1)
HSIO at Poynting
basement
Top-right: HSIO
and Interface
Board.
Bottom-left:
One-hybridpanel from
Liverpool.
Flat-ribbon
cable carries
‘Clk, Control,
Gnd and
Dataout’ signals
(4 LVDS-pairs)
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Test system with Hybrid (3)
The Hybrid under
test (Cooling fan
moved away)
Left-hand
connector:
Datalines (8 LVDS
channels).
Extra power input
for LVDS drivers
(3.3V, 0.26A)
Right-hand
connector: Power
input 3.3V
(drawing
4.4-4.8A). Serial
powering.
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Simon‘s Work in the Clean-Room:
Gluing and Curing
Gluing: Simon has performed a large number of tests applying glue using
mechanical jigs from Liverpool.
Problems encountered: Too much or too little glue at each chip, esp glue
unequally distributed, in worst case leaking - could touch wire-bonds !.
Simon visited Liverpool in July.
One crucial problem identified: One jig was slightly bent, now replaced.
Procedure needs to be ‘learned’, esp how to swipe over jig to distribute glue
(current best results: ‘one chip(-pair) at a time, back and forth once’)
Now: Gluing ‘Glass-ASICs’ (same size and similar weight to real ASIC).
“Curing (chemistry): From Wikipedia, the free encyclopedia
Curing is a term in polymer chemistry and process engineering that refers to
the toughening or hardening of a polymer material by cross-linking of
polymer chains, brought about by chemical additives, ultraviolet radiation,
electron beam or heat.”
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Ideas for improvement of curing procedure
With current materials (two vacuum jigs available, which can’t be put next to
each other on a panel due to clearance), only two hybrids could have chips to
be glued to them at the same time (ie 2 out of the 8 on each module).
Then follows a 24h curing period at room temperature under continuous
vacuum !
Simon is thinking about how this can be optimised. Method called ‘Soft Cure’,
for 2 hours: Glue still ‘soft’ inside (pokeable), but hard enough to support
chips (ie not easily movable under sheer force). Helped by ‘lightly’ heating
to 30C-40C, using heating plate to be made in our workshop.
Ideally could shorten time needed for one module from 4 days (with long
waits) to 1 day (with much less waiting).
Sheer-testing very useful to quantify curing stage (“epoxy crosslink”)
Info from Liverpool: New hybrids are ‘copper balanced’, ie ‘heavier on the
sides’, so don’t bend as much. May not even need vacuum during curing.
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Next Steps
Simon is soon moving to gluing and curing real ASICs – we have a lot of
‘old’ prototypes, ABC-N 250, cut as dies (from Glasgow)
Continuing with test system setup for hybrid, esp run more complex tests,
called ‘StrobeDelay’ and ‘3PointGain’. Discuss results with experts (at RAL,
Liverpool)
Probably connect and test one of the hybrids we’ve assembled in B’ham
Further production preparations on-going:
New power-supply units purchased by the UK groups (remotecontrollable: TTI CPX400DP), B’ham will receive one, needs to be
integrated into HSIO test system, s/w can then control voltage/current.
Simon’s ideas for curing process optimisations under discussion with UK
colleagues
John and Juergen are offering a Yr4 project on hybrid tests,
ie practical part of that project to start January ’14
Next Generation ABC-N chip on its way: ABC-N 130. In Birmingham about
end of year ? UK colleagues are designing new testboards, hybrids, s/w
interface.
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