Transcript Slides
ISPD 2005 ISPD - 2005 A New Era for CAD Gary Smith Chief Analyst Design & Engineering The Automation of RTL Design 2005 The IC Implementation Tool Set automated RTL input to GDS II The RTL Functional Verification Tool Suite automated RTL input to GDS II But GDS II is no longer sufficient. The Automation of the RTL Methodology (from DQ@DAC 2005) Moved to the R T L Intelligent Test Bench ES Level V e r i f i c a t i o n RTL Simulation Formal Verification Formal Analysis Acceleration and Emulation RTL Design Tools GDS II Sign-Off Silicon Virtual Prototype Physical Synthesis DFT Timing, Signal-Integrity and Power Analysis IC Place and Route GDS II ? RTL Sign-Off I C Just becoming I m p l e m e n t a t i o n Reality The IC Implementation Toolset (from DQ@DAC 2002) This is the RTL to GDS II tool flow The functions within the toolset (as a minimum) include logic synthesis; timing, signal-integrity and power analysis; probably DFT and clock tree synthesis; IC place and route (final route is being questioned by some ASIC vendors) The market has been all but wrapped up by Synopsys, Magma and Cadence What Happened ? Tool Set IC Implementation ESL GDS II DFM Correction & IC “re”-Layout Mask Shop But it Didn’t Yield !!! The COT Crisis at 130 nm. - The August 2001 awakening. Who’s Responsible !!! - The Designer - The Foundry - The Mask Shop will fix it ! But will they ? The Era of Disaggregation The 1990s were the Cream Puff era of Semiconductors. Plain old vanilla CMOS was king. Other processes, such as Silicon on Insulator and GaAs, were only niche players. Process improvements were all incremental. The Foundry model grew rapidly. The RTL Methodology drove design the entire decade. It was all so easy. Back to the Future ! This Decade is looking more like the 1980s. Process R&D and Device Physics are a vital part of an IDM’s competitive profile. Will the Foundries be laggards ? Is this the end of CMOS, at least plain old vanilla CMOS ? What does the new transistor look like at 45 nm ? Engineers are moving up to the ES Level of design. Competitive Re-aggregation IDMs and Foundries are moving the Mask Shop back In-House. ASIC Vendors are doing a majority of the IC Layout InHouse again. Twenty Seven Percent of the designers are using some In-House developed tools. Mainstream OEMs are looking for ASIC vendors to take an RTL design Hand-off. Is COT a shrinking business model ? Will the IDMs/Foundries buy up the DFM vendors to keep their new process information proprietary ? The Migration of Design Engineers SoC Design Opportunities are Driven by Applications ESL RTL CAD SoC Implementation Challenges are Driven by Silicon Today’s Challenges and Opportunities ESL CAE RTL CAD DFM Number of Engineers 90,000 79,655 80,000 70,140 70,000 60,000 54,068 56,745 47,279 50,000 40,000 30,000 20,000 11,930 12,658 13,430 14,249 15,118 2001 2002 2003 2004 2005 10,000 0 ASIC IC Layout The IC Layout Team comes to the Rescue The Mask Shops are facing shrinking business and shrinking margins. The Design Team just learned circuit design; they aren’t ready for Layout issues. The IC Layout team was supposed to go away with the new IC Implementation Tool Sets. Now they are the second fastest growing EE segment. The Migration of DFM Technology There are three DFM markets. - The Fab engineer - The IC Layout Engineer - The Design Engineer Tools for the FAB engineer will be a specific market, but fairly small. - And no they won’t pay royalties. The IC Layout Engineer will be the main market. The Design Engineer will use tools that incorporate the last generation of DFM tools and methods. A New Era for CAD So CAD won’t go away “as expected”. “If” the EDA industry provides the tools “on time” it will continue to be a growing market. “If not” the tools will increasingly be built In-House by the Semiconductor vendors. There is no reason to expect that the CAD market won’t continue to supply tools once we enter the nonsilicon era of Semiconductors.