Transcript High-level ATPG for Early Power Analysis

Are classical design
flows suitable below
0.18m?
ISPD 2001
Wolfgang Roethig
Senior Engineering Manager
EDA R&D Group
NEC Electronics Inc.
WR0999.ppt-1
Classical Design Approaches
Full-custom design
• hand-craft the design,
transistor-level analysis
• time-consuming
methodology, usable only
for standard products
Low-end ASIC
• automated design
process, huge margin to
guarantee functionality
• fast TAT, yet sub-optimal
use of process technology
High-end ASIC design must bridge the gap
• fast TAT through automation, yet more sophisticated tools
• aggressive design, but still sign-off guarantee
April 2 2001
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New ASIC design issues
How to partition a
complex SOC design into
manageable blocks?
How to analyze and
reduce chip power
consumption?
How to check the entire
design for localized
voltage drops?
How to calculate and fix
timing in the presence of
crosstalk and noise?
How to ensure
reliability against
electromigration and
hot electron effects?
How to guarantee
manufacturability by
correct layout?
A VDSM design flow must solve all these issues
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Example: crosstalk
Two signals on adjacent wires switch simultaneously
D delay % @ wire length (3rd metal in 0.18u)
victim
aggressor
2x strength
8x strength
2x strength
8x strength
+ 70 % @ 0.5 mm
+ 100 % @ 1 mm
+ 20 % @ 0.5 mm
+ 40 % @ 1 mm
+ 70 % @ 0.5 mm
+ 100 % @ 1 mm
+ 30 % @ 0.5 mm
+ 40 % @ 1 mm
+ 10 % @ 1 mm
+ 60 % @ 3 mm
+ 0 % @ 1 mm
+ 10 % @ 3 mm
+ 40 % @ 1 mm
+ 90 % @ 3 mm
+ 10 % @ 1 mm
+ 30 % @ 3 mm
routing pitch
single
double
single
double
Delay increases up to 100% with single pitch
2x drive aggressor affects even 8x drive victim
Delay increases up to 40% even with double pitch
Significant effect even for 0.5 mm wire
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Example: power and current density
0.35m
0.25m
0.18m
supply voltage
3.3 V
2.5 V
1.8 V
power / gate / MHz
0.07 mW
0.04 mW
0.02 mW
max. # gates
max. clock frequency
6 Meg
120 MHz
12 Meg
230 MHz
34 Meg
450 MHz
Power / Power(0.35m)
1
2.2
6.12
Current / Current (0.35m)
1
2.9
11.3
Technology
max. numbers are absolute technology limits
power = # gates x frequency x power / gate / MHz
current = power / supply voltage
• Power consumption in 0.18m 6 times higher than in 0.35m
• Current density in 0.18m 10 times higher than in 0.35m
• Therefore dramatic increase in electromigration
and voltage drop effects
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Reliability and Manufacturability
• More complicated rules for design tools
Technology
Manufacturability
0.35m
No design issue
0.25m
Electromigration &
hot electron check
for cells
Global antenna rules
0.18m
Electromigration &
hot electron check
for cells,
avg. current limit
Electromigration &
hot electron check for
cells and interconnect,
avg. and peak current
limit
Layer-specific
antenna rules
0.13m
April 2 2001
Reliability
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No design issue
Layer-specific
antenna rules and
metal density rules
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Consequences
• Signal integrity effects can not be handled in isolation
– crosstalk is the effect of multiple interacting signals
– voltage drop is a system-level effect
– reliability and manufacturability rules reduce the degrees of
freedom for timing optimization
– timing affects xtalk and vice versa
– timing affects power and vice versa
• Design tools need to be signal-integrity literate
– coherent and concurrent design and analysis of all signal
integrity effects is required
– transistor-level analysis is not feasible
– need higher level abstract analysis models
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2000
2002
0.25m
0.18m
0.13m
RTL
RTL
Synthesis
RTL
Synthesis
RTL Planning
Gate
Gate
Physical Synthesis
Placement
Routing
Timing
check
Gate-level planning
Physical Synthesis
Timing Optimization
Routing
2MG
100MHz
Timing, Power,
Signal Integrity
Optimization
Routing
Signal Integrity
Check&Repair
Signal Integrity
Correctness
10MG
200MHz
April 2 2001
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Timing, xtalk, antenna,
electromigraqtion
1998
Power consumption,
Voltage drop
Changing Design Environment
30MG
400MHz
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Need for advanced library modeling
• Design flow will need common or compatible analysis backplane
• Technology library and its components (cells, blocks, wires) need
to be characterized
– timing and power are not sufficient
– crosstalk delay and noise, electromigration, hot electron effect,
manufacturability must be described
• Models must be
– accurate for high performance ICs
– efficient for analysis and optimization
– suitable for designers (model specification) as well as for
characterization, design and analysis tools (model usage)
• The Advanced Library Format (ALF) provides a solution
– Already proliferating in the industry
– Emerging IEEE standard (see www.eda.org)
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Conclusion
• Classical ASIC design flow is changing
– increasing complexity: hierarchical design
– decreasing geometry: signal integrity
• VDSM technology requires more aggressive design
– not enough room for guard bands: physics are too severe
– not enough time for manual work: designs are too large
• New generation of design tools and flows
– concurrent design and analysis for timing, power, signal
integrity, manufacturability using advanced library models
• Merge of design flows
– SOC contains ASIC-style blocks and custom blocks
– Hierarchical design, analysis and optimization enabled by
abstract models of the blocks
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