Transcript Low Power Design for Wireless Sensor Networks

Low Power Design for Wireless
Sensor Networks
Aki Happonen
Table of Contents
• Introduction
• Digital Design
• RF Design
• Conclusions
Introduction
• Many cases wireless
sensors are deployed to
remote location without
capability to replace
battery.
•One of the key
elements for distributed
sensors is long lifetime
covering both
reliability and energy
efficiency.
• This presentation covers
low power design
methods – focus on
digital design
source:http://bwrc.eecs.berkeley.edu/People/Faculty/jan/presentations/hotchips1.pdf
Digital Design - Efficiency
• The most efficient
solution is
Application Specific
IC while the worst
energy efficiency is in
synthesizable
processors
Energy
Efficiency
MIPS, MOPS, Benchmarks /
mW,
• One key element in
digital design is
energy-flexibility
trade-off
ASIC
Reconfigurable
Logic
DSP & ASIP
Synthesizable RISC
Flexibility
[J. M. Rabaey 2000]
Digital Design – Asynchronous
• Operating voltage is the key element in
energy consumption – lower the voltage
lower the power consumption
• Asynchronous design is one method to
adopt lower operating voltage and lower
clock frequency
• Two methods for data path: single rail and
dual rail
Digital Design – Single Rail
• In single-rail design
controller generates
initial request signal.
• Request signal goes
through delay that is
matched to processing
delay and it is also
latching signal for
output.
• Acknowledge is
generated by delaying
request signal by the
time latching the output
takes
• An advantage of single rail
design is that synchronous
designs’ blocks could be
used so data paths have good
area constraints.
Digital Design – Dual Rail
• In dual-rail design data
is encoded using two
wires for each bit. Codes
“01” and “10” present
“1” and “0” data values
and code “00” represents
spacer or idle state.
• This is robust method
that guarantees correct
operation with arbitrary
delays in the circuit or
logic.
• A disadvantage of dualrail logic is larger area
due the two wires per bit
encoding
Dynamic Voltage Scaling (DVS)
• DVS allows the
processor operating
voltage, and frequency
to be reduced when
workload levels are low
• Challenge: How to get
the optimum voltage?
• Huge power saving
potential: 53% savings
[Sinha A. et al]
• Current consumption is
not dependent on code –
only voltage and clock
frequency matters
Processing Load
• One important issue
in power
management is to
minimize processing
activity variation.
• Battery lifetime
decreases as a
function of increase
in workload variance
even if the average
workload remains
fixed.
RF Design
• Power amplifier dominates
total power budged if the
transmission range is more
than 10 meters
• But short-range
communication having
• Table shows low power
gigahertz carrier frequency
design examples for BT
the radio the frequency
synthesizer dominates
power rather than the
actual transmit power
• In packet based
communication the startup time of radios start to
dominate in energy
consumption
Conclusions
• The most attractive technology to reduce power
consumption is dynamic voltage scaling.
• In digital design energy per operation scales
with technology but communication energy per
transmitted bit does not scale at the same rate.
• Compute do not communicate.
• In the end implementation selections will be
minor issue if the system level constraints are
wrong.