Transcript Impact of RET on Phycisal Design ISPD 2001 April 2, 2001

Impact of
RET on
Physical
Design
ISPD 2001
April 2, 2001
F.M. Schellenberg, Ph.D.
Calibre RET Group
Luigi Capodieci, Ph.D.
ASML MaskTools
Agenda


Agenda
Resolution Enhancement Technology (RET)
– Lithography Basics
– RET: OAI, OPC, PSM, and all that


Insertion in Process Flows
Impact on Physical Design
– OAI
– OPC
– PSM


Importance of a “Target” layer
Conclusions
F.M. Schellenberg / ISPD 2001 / April 2, 2001
2
4
Lithography Basics
UV
Laser
Illumination
Mask
Lens

All IC layers are formed
by Lithography

The light interacts with
a reticle (aka mask)
and the lens to form
a reduced
image in
100
photoresist
Wafer
F.M. Schellenberg / ISPD 2001 / April 2, 2001
3
Lithography Basics
• High spatial frequencies (dense lines) scatter at larger angles.
• The lens acts as a low-pass filter for high spatial frequencies
F.M. Schellenberg / ISPD 2001 / April 2, 2001
4
Lithography Basics




Fine pitches diffract at higher angles
The lens acts recollects light onto the wafer
The lens acts like a low pass filter
“DC” light passes directly through the lens
– No contrast
– No image
– Wasted light
F.M. Schellenberg / ISPD 2001 / April 2, 2001
5
Lithography Basics


4
The light interacting
with the mask is a wave
3
B
Any wave has certain fundamental
properties
–
–
–
–

2
Wavelength (l)
1
Direction
0Amplitude
Amplitude
-1
Phase
-2
l
RET is wavefront-3engineering
to enhance lithography
-4
-20
0
20
by controlling these
properties
F.M. Schellenberg / ISPD 2001 / April 2, 2001
Direction
Phase
40
60
6
80
100
4
Wavefront Engineering: Direction
3
B
2
l
Direction
1
Amplitude
0
-1
Phase
-2
-3
-4
-20
0 / April 2, 20
F.M. Schellenberg
/ ISPD 2001
2001
40
60
80
7
100
Wavefront Engineering: Direction


Regular Illumination: Uniform disc
Off-Axis Illumination: e.g. Annular
Lens
lens
F.M. Schellenberg / ISPD 2001 / April 2, 2001
Lens
8
Wavefront Engineering: Direction

Many off-axis designs
– Annular
– Quadrupole / Quasar
– Dipole

or
+
See your local stepper/scanner supplier
F.M. Schellenberg / ISPD 2001 / April 2, 2001
9
4
Wavefront Engineering: Amplitude
3
B
2
l
Direction
1
Amplitude
0
-1
Phase
-2
-3
-4
-20
0 / April 2, 20
F.M. Schellenberg
/ ISPD 2001
2001
40
60
80
10
100
Wavefront Engineering: OPC


Optical and Process Correction (OPC)
for Amplitude Control
Modifies layout to compensate for
process distortions
– Add light where needed
– Subtract light where not wanted
– Add non-electrical structures to layout to
control diffraction of light
F.M. Schellenberg / ISPD 2001 / April 2, 2001
11
Wavefront Engineering: OPC
Mask layout
F.M. Schellenberg / ISPD 2001 / April 2, 2001
Wafer result
12
4
3
Wavefront Engineering: Phase
B
2
l
Direction
1
Amplitude
0
-1
Phase
-2
-3
-4
-20
0 / April 2, 20
F.M. Schellenberg
/ ISPD 2001
2001
40
60
80
13
100
Wavefront Engineering: PSM

Phase Shifting Masks (PSM)

Etch topography into mask
– Creates interference fringes on the wafer
– Interference fringes can be extremely small

Make mask material phase shifting
– “Attenuated” PSM
F.M. Schellenberg / ISPD 2001 / April 2, 2001
14
Wavefront Engineering: PSM
Mask
L  0.25
l
NA
For conventional steppers:
l248 nm, NA=0.63
L  98 nm
F.M. Schellenberg / ISPD 2001 / April 2, 2001
15
Wavefront Engineering: PSM


Interference effects
boost contrast
Phase Masks can
make extremely
small gates
90 nm
SEM image courtesy of IMEC

Phase Masks can
double resolution
0°
180°
– 2X finer pitches
F.M. Schellenberg / ISPD 2001 / April 2, 2001
16
So What?

RET not done in isolation

Selection of RET technique carries an
impact on design rules / layout restrictions
F.M. Schellenberg / ISPD 2001 / April 2, 2001
17
Insertion points of RET

OAI:
– Inserted into Lithography Stepper

OPC
– Typically inserted at Physical Verification


Verification modified to include process simulation
PSM
– Modify P&R rules to allow finer pitches
– Insert at P&R , Physical Verification, or
Mask Data Preparation
F.M. Schellenberg / ISPD 2001 / April 2, 2001
18
Impact on Physical Design
OAI
OPC
PSM
F.M. Schellenberg / ISPD 2001 / April 2, 2001
19
Impact on Physical Design: OAI

Off axis amplifies certain pitches at the
expense of the others.
Concept of “Forbidden” pitches
Quadrupole
Illumination
Depth of Focus (a.u.)

Quadrupole
Conventional
100
150
200
250
300
350
400
Half Pitch
(nm)
Half
Pitch
(nm)
Graph reference: Noguchi, M. et al. “Subhalf Micron Lithography System with Phase Shifting Effect”,
in Optical/Laser Microlithography V, Proc. SPIE Vol. 1674 (1992), 92-104.
F.M. Schellenberg / ISPD 2001 / April 2, 2001
20
Impact on Physical Design: OAI
Without SRAF
1.5
Quasar illumination
NA=0.7
1
Isolated
0.5
Acceptable
Unacceptable
Dense
Quasar
Illumination
Depth of Focus (mm)
130 nm lines, printed
at different pitches
0
200
400
600
800
1000
1200
Pitch (nm)
Graph reference: Socha et al. “Forbidden Pitches for 130 nm lithography and below”,
in Optical Microlithography XIII, Proc. SPIE Vol. 4000 (2000), 1140-1155.
F.M. Schellenberg / ISPD 2001 / April 2, 2001
21
1400
Impact on Physical Design: OAI
Isolated
Quasar
Illumination
Dense
45° lines vanish
110 nm lines
Quasar illumination NA=0.7
F.M. Schellenberg / ISPD 2001 / April 2, 2001
22
Impact on Physical Design: OAI

Quasar / Quadrupole Illumination
– Amplifies dense 0°, 90 ° lines
– Destroys ±45° lines

Dipole Illumination
– Horizontal Dipole prints only Vertical Lines
– Vertical Dipole prints only Horizontal lines
– Must decompose layout for 2 exposures

Vertical mask, horizontal mask
F.M. Schellenberg / ISPD 2001 / April 2, 2001
23
Impact on Physical Design
OAI
OPC
PSM
F.M. Schellenberg / ISPD 2001 / April 2, 2001
24
Impact on Physical Design: OPC

OPC changes layout dramatically

OPC does not change design
F.M. Schellenberg / ISPD 2001 / April 2, 2001
25
Impact on Physical Design: OPC
Designed
Layout
Mask
Final
Layout
F.M. Schellenberg / ISPD 2001 / April 2, 2001
Wafer
26
Impact on Physical Design: OPC
Original Designed Layout
Layout with OPC
Graphics courtesy of IBM
F.M. Schellenberg / ISPD 2001 / April 2, 2001
27
Impact on Physical Design: OPC
SEM image courtesy of IBM
F.M. Schellenberg / ISPD 2001 / April 2, 2001
28
Impact on Physical Design: OPC
Graphics & SEM image courtesy of IBM
F.M. Schellenberg / ISPD 2001 / April 2, 2001
Simulation based check
29
Impact on Physical Design: OPC



OPC provides an automatic layout fix to
achieve the target layer on the wafer
With simulation based checking,
design rules can be more aggressive
Physical Verification becomes
process-aware
– Expands to add OPC
– Verifies the results with process simulation
F.M. Schellenberg / ISPD 2001 / April 2, 2001
30
Impact on Physical Design
OAI
OPC
PSM
F.M. Schellenberg / ISPD 2001 / April 2, 2001
31
Impact on Physical Design: PSM

PSM allows true resolution enhancement
– Thin gates 90 nm wide in 180 nm process
– Pitch doubling

Line size / pitch defined in
– Libraries
– Routing algorithms

90 nm
Drives insertion to P&R
SEM image courtesy of IMEC
F.M. Schellenberg / ISPD 2001 / April 2, 2001
32
Impact on Physical Design: PSM

Maskmaking concerns for PSM
–
–
–
–

Phase etch effects: linewidth imbalance
No inspection technique
No repair technique
Desire to minimize final phase area
Drives phase assignment to the last
possible moment
F.M. Schellenberg / ISPD 2001 / April 2, 2001
33
Impact on Physical Design: PSM

Best compromise:
– Phase compliant Libraries, design rules

Phase assignment done at Verification
– Allows PSM with OPC to be verified together
– Verification includes mask manufacturing rules
(e.g. imbalance).
F.M. Schellenberg / ISPD 2001 / April 2, 2001
34
Impact on Physical Design

All RET make major changes to the layout

The “design” remains unchanged

Main consequence of RET:
– Divorce between Design and Layout
F.M. Schellenberg / ISPD 2001 / April 2, 2001
35
Impact on Physical Design
“Target” Layer
F.M. Schellenberg / ISPD 2001 / April 2, 2001
36
“Target” Layer

All RET packages have
one common assumption:
– The layout presented is the
desired structure for the wafer

In practice, this is NOT true.
F.M. Schellenberg / ISPD 2001 / April 2, 2001
37
“Target” Layer





Design Rules have evolved to
“make things work”
These include compensations for
physical phenomena (pre OPC)
The phenomena ebb and flow with process;
The rule remains as long as things work
With OPC, things may no longer work
– The rules need to be reexamined
F.M. Schellenberg / ISPD 2001 / April 2, 2001
38
“Target” Layer

Example: Historical rule on line extension
Truly desired on wafer

Layout according to design rule
OPC software assumes the layout is the target,
and adds OPC to the old OPC extension
OPC on the OPC
F.M. Schellenberg / ISPD 2001 / April 2, 2001
39
“Target” Layer: SRAM Example
F.M. Schellenberg / ISPD 2001 / April 2, 2001
40
“Target” Layer: Example of Embedded OPC LI Design
Hand Applied OPC:
A = 240nm
B = 255nm
C = 270nm
Bit Cell
Slide courtesy of LSI Logic
F.M. Schellenberg / ISPD 2001 / April 2, 2001
41
“Target” Layer: Poly Layer De-OPC Rule Deck
Generic De-OPC Rule
// input layers are uppercase
LAYER NISLAND_LAYOUT 2 //nisland -original input
LAYER PISLAND_LAYOUT 3 //pisland -original input
LAYER POLY_LAYOUT
4 //poly -original input
LAYER CONTACT
5 35
island = Or NISLAND_LAYOUT PISLAND_LAYOUT
islandCE = Coincident Edge island endcap1
islandCEa = Length islandCE > 0.15
gate = And POLY_LAYOUT island
gate1 = Size gate By -0.08
gate2 = Size gate1 By 0.08
endcap1 = Not POLY_LAYOUT gate2
endcap2 = Not Enclose endcap1 CONTACT
endcap2a = Area endcap2 < 0.15
endcap3 = With Edge endcap2a islandCE == 1
endcap4 = With Edge endcap3 islandCEa
realEndCap = vertex endcap4 > 4
OPC Free Cell
'endcap_flag_fix'
{
poly = Not POLY_LAYOUT realEndCap
islandCEb = Coincident Inside Edge poly island
Expand Edge islandCEb Outside By 0.15
}
Slide courtesy of LSI Logic
F.M. Schellenberg / ISPD 2001 / April 2, 2001
42
“Target” Layer Plan: De-OPC on Bit Cells
Cell Libraries
OPC Free
Cell Libraries
Memory
De-OPC
Memory
I/O
De-OPC
I/O
Compiler
“Target” Layout
Memory
Analog
De-OPC
Analog
Mixed
Signal
De-OPC
Mixed
Signal
Etc.
De-OPC
Etc.
Analog
Mixed
Signal
I/O
DRC/LVS
Process-based OPC
Slide courtesy of LSI Logic
F.M. Schellenberg / ISPD 2001 / April 2, 2001
Tape Out
43
“Target” Layer Conclusion





Design rules are riddled with historical OPC
DON’T DO THAT!
With systematic OPC now part of the flow,
it will do the heavy lifting
Consciously clean up libraries and design
rules to create the actual “target” layout
If this is not done,
mysterious failures will continue
F.M. Schellenberg / ISPD 2001 / April 2, 2001
44
Conclusions

Selection of RET is mandatory for future
progress down Moore’s Law
– It’s not going away

RET style has an impact on layout
– Design and layout become very different

Design to a “Target” layer
– Produce a layout that shows what is really desired
– Allow RET to do its job
F.M. Schellenberg / ISPD 2001 / April 2, 2001
45
Acknowledgements





Emile Sahouria, Olivier Toublan
Mentor Graphics
Bob Socha, ASML
Lars Liebmann, IBM
George Bailey, LSI Logic
Kurt Ronse, IMEC
F.M. Schellenberg / ISPD 2001 / April 2, 2001
46
Thank you for your attention.
F.M. Schellenberg / ISPD 2001 / April 2, 2001
47
F.M. Schellenberg / ISPD 2001 / April 2, 2001
www.mentor.com
48