Transcript Churning the Most Out of IP-XACT for Superior Design Quality

Churning the Most Out of IP-XACT
for Superior Design Quality
Ayon Dey
Lead Engineer, TI
Anshuman Nayak
Senior Product Director, Atrenta
Samantak Chakrabarti
Senior Manager, Atrenta
Samiullah Shaik
Applications Engineer, Atrenta
Introduction/Agenda
What IP Metadata is useful
• Power/voltage domain, clock,
resets, default values, port typesdft/interrupts/dma etc
How can this Metadata be extracted
• Directly from IP RTL
• While doing IP packaging by the
module designer
How is this metadata used
• SoC Integration: Intelligent Integration
• Integration quality checkers
• Generators (eg CPF from IPXACT)
2
SoC Integration Challenges
• Integrate SoC (IP>100) with
minimum design resources
Productivity
Challenge
SoC Integration
SoC integration is not limited
to just connecting IPs
• Reduce number of
IP bugs, verification
cycles
• Need to do it:
Correct by
construction
Complexity
Gordon Moore
• Higher integration
• Need to increase:
Reuse
• Power management
• Do it Quickly
• Numerous clock
domains
Time to Market
• Increase efficiency
by Enabling
Downstream flows
• Accelerate SoC development
cycle
• Quick Spins
3
Common Uses of IPXACT
Documentation
Software
• Implementation
Specifications
• Generation of System
memory map
• Header files
IPXACT
SoC Integration
• Generation of RTL netlists
Design/Integration Metadata
• Component/Component Instances
• Bus Interfaces/Interface connections
• Ports/AdHoc connections
• Design Configurations
• Filesets
• Registers
Verification
• Generate C tests
• Software header files
4
What IP Metadata is Useful
• A few examples of what can be added as metadata in IPXACT are
below
• Supported by IPXACT 1685
– Clock attribute (Mention the
port as clock and if it’s a clock
the frequency/pulse width
value)
– Default value
– Clock driver/signal
characteristics (related clock
pin for that port)
– Load/drive cell strength
specification
– Constraints attribute which
includes
• Not supported in standard
IPXACT
–
–
–
–
–
–
Power domain attribute
Voltage domain attribute
Reset attribute
DFT information
Interrupts
DMA
• Can be saved as IPXACT
vendor extensions
• Timing constraints
• Drive constraints
• Load constraints
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How Do I extract Metadata into IP-XACT?
How do I use it?
Packaging
SpyGlass®
DataSheet
RTL
IP-XACT
Incremental
Packaging
Atrenta GenSys®
Clock constraints
(optional)
Rich IP-XACT storing packaged
RTL and other design property
Checkers
Error: Clock pin connected to
non-clock pin!
Error: Reset pin connected to
non-reset pin!
Generators
Module IP1 Pin “clk”
connected to Module CLK_IP
Pin “clk_25_mhz”. Connection
done by matching frequency
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Examples of Checkers and generators
• Clock and non-clock pin short error check generator
• Reset and non-reset pin short error check generator
• Clock ports automatic connection based on clockfrequency property in IPXACT
• Text Report generators
• Clock/Reset connectivity generator
• Generate verification assertions for protocol checks
• CPF macro-model generator
• Power Cells insertion generators
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Generate a CPF Macromodel from IPXACT
Generators
Execute the
custom
generators
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Text Report Generators
• Reports
– Audit report
• instance, port
interface
summary,
connectivity
percentage or
health check
– Design difference
report between
two snapshots
– Design resources
• black-boxes, hard
macros etc.
– Dense structures
• instances with very
high pin count
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Power Cells Insertion Generator
Power Information
• IP Instance – Power/Voltage domain association
• Power cells (isolation/levelshifters/switch cells) and their control
info
top
IPXACT
Voltage 1
• Default Values for all IP outputs
Generator
Power 1
Pd1_ip1
Pd1_ip2
IP1
IP2
IP3
IP4
Voltage 2
P
M
Power 2a
P
M
Pd2a_ip1
Power 2b
P
M
Pd2a_ip2
Pd2b_ip1
Pd2b_ip2
Power Managed SoC
IP5
• Hierarchical RTL netlist
Connectivity IPXACT
• Power cells inserted in RTL
• SoC where all IPs are
connected
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Power management Generator Metrics
•
•
•
•
•
No of Power Domains = 6
No of Voltage Domains = 2
No of level Shifters = 2500
No of Isolation cells = Low (26500), High (4520), Latch (260)
No of IP instances in each PD.
–
–
–
–
–
–
PD1 = 47
PD2 = 26
PD3 = 4
PD4 = 3
PD5= 1
PD6 = 6
• Run Time = 20mins
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Other Results
# Designs this
feature being Used
# Issues found while
SoC integration using
IPXACT checkers
If not, this issue
would have been
found in
Relative
Effort
>10
Average of 15 per
SoC RTL release
Power Aware
RTL simulations
10
>10
Average of 12 per
SoC RTL release
Lint, Verification
3
Check clock pin connected to nonclock pin
1
Total of 3
RTL simulation
2
Check reset pin connected to nonreset pin
1
0
RTL simulation
2
Active high signal connected to Active
low signal
1
13
RTL simulation
5
Features
Insertion of power management
structures while doing SoC RTL
development
Check input not connected
Used in # of
Designs
Traditional Approach
Relative
Effort
>10
Connectivity PercentageManual
Rest All - Lint
3
Clock ports automatic connection based
on clock-frequency property in IPXACT
1
Manual
5
Reset Pin automatic connection based on
rest attribute in IPXACT
1
Manual
5
Generator
Text Report Generators to check
connectivity percentage, unconnected
ports, multiple drivers
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Conclusion
• What was new?
– We have shown how IP-XACT can be used beyond the conventional way
– We used a mixture of tools like SpyGlass to extract metadata into IPXACT automatically from RTL with minimal user inputs
• Then used this IP-XACT at SoC level to develop checkers and generators
– Some of the generator outputs (like CPF macromodel, or clock
constraints, etc.) can be used in other downstream flows
• E.g., verification, synthesis, static low power checks.
– These techniques ensure that metadata is captured right at the time of IP
design, by the designer himself
• Ensures minimum loss of data across handoffs and saves verification time
• Some properties that are not part of IP-XACT standards currently, but
can be considered in future versions of IP-XACT:
- Power domain attribute
- Voltage domain attribute
- Reset attribute
- DFT information
- Interrupts
- DMA
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