Transcript No Slide Title

Semiconductor Processing (front-end)
Stuart Muter
617.371.3853
[email protected]
12/02/2002
Semiconductor Processing
Agenda: An overview of the key steps in semiconductor processing (how to make one of Stuart’s
wafers).
A lot of information is in the packet, we will not be able
to cover it all.
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Table of Contents
Section A
Introduction to Semiconductor
Manufacturing
Section B
Key Processing Steps
- Deposition
- Etch
- Lithography
- Doping and Anneal
- CMP
Section C
3
Future Trends
SECTION A:
Introduction to Semiconductor
Manufacturing
Front End Processing
Key Steps
•Deposition
- CVD
- PVD
- Oxidation
•Etch
•Lithography
•Doping and Anneal
- Diffusion
- Ion Implant
- RTP
•CMP
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Moore’s Law
Transistor density doubles every 2 years
Moore’s Law
Source: www.intel.com
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Wafer Sizes
Source: Design News
IC Feature Size Trends
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State of the Art Semi Device
•0.13 micron critical dimension (human hair diameter is
approx. 100 microns).
•7 metal layers
•25 mask steps
•300 - 400 process steps
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State of the Art Fab
•300mm wafers
•$2-3 billion cost
•wafer cycle time: 30 -80 days
•WIP: 20 - 40K wafers
•Full material automation
•Cleanroom: Class 10 or 100
•Mini-environment: Class 0.1
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Semi and Semi-Equipment Industries
Market Segmentation
Worldwide Semiconductor
Market
Source: WSTS 11/01
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Semi-Equipment Industries
Wafer Fab Equipment Spending
WFE Revenue Forecast by Equipment
Segment ($ Millions)
Equipment Segment
Worldwide Fab
Change (%)
Total Lithography/Track
Total Removal Processes
Total Deposition
Total Diffusion/RTP
Total Ion Implantation
Total Process Control
Total Process Control
Total WFE
Source: Gartner Dataquest (July 2002)
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2001
23,654
-28.6
5,750
6,177
4,920
789
908
3,578
19
23,654
2002
18,929
-20
4,999
4,687
3,937
639
708
2,761
28
18,929
2003
26,908
42.1
7,603
6,375
5,784
884
987
3,480
54
26,908
Device Manufacturing
0.5µ CMOS Process Flow
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Fab
Integrated Circuit Manufacturing Process
The “big picture” process
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SECTION B:
Key Processing Steps
Blanket Metal Deposition
Typically PVD or MCVD
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Physical Vapor Deposition
•Preferred conductor
deposition technology
•Barrier and seed layer for Cu
•DC/RF magnetron sputtering
•Conductors:
- Al (interconnect), Ti, TiN,
TiW
(barrier and ARC), W
(vias), Cu
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