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Analysis and Reduction Soft
Delay Errors in CMOS Circuits
Balkaran Gill, Chris Papachristou,
and Francis Wolff
Department of Electrical Engineering
and Computer Science.
Case Western Reserve University
Cleveland Ohio USA
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Outline
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Introduction.
Soft delay phenomenon.
Soft delay modeling.
Soft delay error analysis and reduction
technique in combinational circuits.
Future work and conclusion.
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Introduction
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Single Event Upsets (SEUs) are due to high
energy particle strikes at sensitive nodes in
CMOS circuits.
These upsets originate from cosmic rays in
outer space and α-particles within the chip.
Soft Error Rate (SER) in CMOS circuits is
projected to increase as the process
technology scales down.
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Introduction (cont’d)
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A particle strike at the sensitive nodes of
combinational circuits results in a glitch
(pulse) which can propagate to the circuit
output and captured by output flip-flops.
A particle strike at the sensitive node during
the signal transition can result in temporary
delay (soft delay) which can violate the
circuit timing.
SEUs in memory cause temporary cell flip.
Semiconductor memories are more
vulnerable than logic.
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Soft Delay Phenomenon
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When a particle strike occurs during the
transition at a node, it can introduce
additional temporary delay.
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Soft Delay Propagation
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Propagation of the soft delay.
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Soft Delay Propagation
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The pulse
generated due
to the particle
strike during
the transition
attenuates
resulting in
soft delay.
Soft Delay Error
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Soft Delay Modeling
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Mixed-mode simulations: Circuit and Device
Simulations.
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Device simulations for Soft Delay
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Particle strike simulations using photogeneration models in DAVINCI.
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Current Pulse Extraction
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Extracted current pulses for various
energies of the hitting particle.
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Soft Delay in ISCAS85 Benchmark
Circuits
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Soft delay at the critical path of ISCAS85
circuits for various hitting particle energies.
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Soft Delay Error Analysis and Mitigation
Flow
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Reducing SDE - Example
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Conclusion
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Found Soft Delay problem and developed
models to analyze its effects.
Verification of the soft delay using mixedmode simulations.
Characterization of the soft delay in
ISCAS85 circuits.
Soft delay error analysis and mitigation
technique.
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Current and Future Work
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Current work
• Soft delay error analysis approach for large
circuits.
• Soft errors analysis in reconfigurable system
(FPGA).
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Future work
• System level node sensitivity analysis
approach.
• Mitigation techniques for soft errors in VLSI
circuits.
• Mitigation techniques for soft errors in SRAM.
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