Transcript SER estimation of SRAM-based FPGAs

Analytical Approach for Soft Error Rate
Estimation of SRAM-Based FPGAs
Ghazanfar (Hossein) Asadi
Test & Reliability Group (TRG)
Department of Electrical & Computer Engineering
Northeastern University
2004 MAPLD/221
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Outline
2004 MAPLD/221
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Problem Statement & Motivation
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Soft Errors Background & Previous work
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Error Models in FPGAs
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SER Estimation
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Experimental Results
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Summary & conclusions
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Problem Statement
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Estimating soft error rate in FPGAs
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The probability of system failure
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For a given mapped design
Mean time to manifest a corrupted conf. bit
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2004 MAPLD/221
Due to soft errors
To primary outputs or Flip-flops
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Motivation
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Need for soft error rate estimation
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Exponential growth of vulnerable bits due to Moore’s law
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High cost of Error tolerant schemes
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To make appropriate cost/reliability trade-offs
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Why an analytical method?
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Where to put redundancy
Previous work: Fault Injection
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Time-consuming / Incomplete / Expensive
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Needs physical prototype board
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Cannot be used in design phases
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Background: Error Definitions
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Soft Errors:
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Intermittent malfunctions of the hardware
Not reproducible
Energetic Particles
 Single Event Upsets (SEUs)
Soft Errors
 (may cause) System Failure
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Previous Work
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Based on Fault Injection (FI)
1. Inject fault
2. Run several workloads
3. Compare results with fault-free circuit
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Exhaustive FI is very time-consuming
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Candidate some locations for FI
Analysis based on statistics
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Previous Work (Cont.)
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Radiation-based fault injection
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Expensive & not commonly used
Needs physical implementation
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Can damage prototype board  Hard error
Simulation-based fault injection
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2004 MAPLD/221
Cannot be used during design phases
Bit-stream alteration
Needs physical implementation
Bridging errors may lead to hard errors
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Outline
2004 MAPLD/221

Problem Statement & Motivation
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Soft Errors Background & Previous work

Error Models in FPGAs
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SER Estimation

Experimental Results

Summary & conclusions
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Error Models in FPGAs
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Memory resources:
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User bits
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Configuration bits
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Flip-flops, RAMs, …
Mux select bits, LUT bits, …
User bits  Transient errors
Config. bits  Permanent errors
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Error Models in FPGAs (Cont.)
 Bit flip
 Permanent error
 Corrected by
reconfiguration
 Bit flip
Transient error
 Can be corrected at the next load
E1
E2
E1
E3
 Short or open circuit
 Corrected by reconfiguration
clk
E2
E3
BlockRAM
F1
F2
F3
F4
LUT
M
ff
M
M M M M
M
M
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Configuration Memory Cell
SEU
(Bit flip)
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© Lima (DAC03)
Virtex (Xilinx)
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Error Models in FPGAs (Cont.)
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Transient errors
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User flip-flops, Logic gates, Block RAMs
Permanent errors (all configuration bits)
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Routing:
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MUX select bits
PIP: Short/Open
Buffer: On/Off
LUT
Control/Clocking Bits
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Error Models in FPGAs (Cont.)
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Only permanent errors considered
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Conf. bits comprise more than
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99% of all memory elements excluding RAM blocks
95% of all memory elements including RAM blocks
Device
# of Config.
Bits
# of FlipFlops
Ratio
XCV50
559,200
3,996
99%
XCV400
2,546,048
22,812
99%
XCV800
4,715,616
43,872
99%
XCV1000
6,127,744
56,832
99%
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Outline
2004 MAPLD/221

Problem Statement & Motivation

Soft Errors Background & Previous work

Error Models in FPGAs
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SER Estimation

Experimental Results
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Summary & conclusions
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SER Estimation
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Traversing structural paths [Asadi04]
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From fault sites to POs
Off-Path Signals: Thin Lines
PO
SEU
PO
On-Path Signals:
Thick Lines
FF
Off-Path Signals
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SER Estimation in ASIC Designs
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S(n): System failure probability (SFP) vector
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Si: SFP given node i erroneous
n: total fault sites
Experiments on ISCAS89 show that:
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Three order of magnitude faster
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Compared to random-input simulation
Average accuracy: 97%
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FPGA vs. ASIC in SER Estimation
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ASIC: transient error
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Only requires propagation probability
FPGA: both transient & permanent errors
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Transient errors: the same
Permanent errors: needs activation as well
Nodes with different error rates in FPGAs
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Fault sites: all nodes
1
1
n1
A
1
B
1
n2
1
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SER Estimation of FPGAs: Steps
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Compute permanent error rates for all nodes
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PRi : the permanent error rate of node i
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Compute netlist failure probability vector
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Ni= failure prob. given node i erroneous
System failure rate vector (S) = PR  N
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n: total number of fault sites
Si = PRi  Ni
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How to Compute Ni?
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Open & stuck-at errors:
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Bridging wired-AND error (nets i and j):
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Ni = [SPi(1-SPj)PPi(0)] + [(1-SPi) SPjPPj(0)]
Bridging wired-OR error (nets i and j):
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Ni = [SPi  PPi(0) + (1-SPi)  PPi(1)] = PPi
PPi: Propagation prob. (the method used for ASIC)
SP: Signal probability is used for activation prob.
Ni = [SPi(1-SPj)PPj(1)] + [(1-SPi) SPjPPi(1)]
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How to Compute PRi?
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PR(n): permanent error rate vector
PRi : r  f
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r: Raw error rate of an SRAM cell
f: Number of all possible errors at node i
n: total number of fault sites
PRAB= 6  r
1
1
1
1
A
B
0
0
1
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System Failure Rate
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For the first clock:
n
SFR  1   (1  S i )
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i 1
For c clock cycles:
n
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SFR  1   (1  PRi  (1  N i ) c

i 1
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The same probability is valid for the next clock cycles
c: Number of clocks checking the state of the circuit
 After particle hit
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Outline
2004 MAPLD/221

Problem Statement & Motivation

Soft Errors Background & previous work

Error Models in FPGAs

SER Estimation

Experimental Results

Summary & conclusions
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Error List
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Mux-open
PIP open
Buffer off
A bit-flip in LUT
Control bit-flip
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Experimental Setup
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Xilinx Virtex 300 (XCV300)
Xilinx Design Language (XDL)
Benchmark: some ISCAS89 circuits
r = raw failure rate for an SRAM cell
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1000 clocks executed for each SEU
Platform: Sun Solaris Ultra-10
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r=0.01 FIT/bit
256 MB Main Memory
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Results: Sensitive Bits
Number of sensitive SRAM bits for each part
Circuit
2004 MAPLD/221
S27
S298
S344
S349
s382
s386
Routing
64
459
536
650
807
714
LUT
68
418
392
520
712
660
Control/
Clocking
40
140
168
187
207
160
Total
172
1017
1096
1357
1726
1534
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Results: Manifestation Time
Mean Time To Manifest (MTTM) errors to outputs
Circuit
S27
S298
S344
S349
s382
s386
Routing
2.07
2.86
2.58
2.91
3.30
3.82
LUT
14.49 20.75 17.33 20.48 22.08 30.07
Control/
Clocking
1.18
1.31
1.36
1.40
1.40
1.77
(Results are in terms of cycles)
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Results: SFR & Estimation Time
System Failure Rate & Estimation Time
Circuit
S27
S298 S344 S349
s382
s386
SFR (FIT)
1.71
9.87
9.99 12.77 16.04 12.11
SP Time (sec)
0.15
0.76
0.91
1.09
1.25
1.05
SFR Time (sec)
0.02
0.09
0.13
0.14
0.19
0.25
Total Time (sec) 0.17
0.85
1.04
1.23
1.44
1.30
Number of Clock cycles: 1000
SP Time: Signal Probability computation time
SFR Time: System Failure Rate computation time
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Summary & Conclusions
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A new approach for SER estimation
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No physical implementation required
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Can be used in early design stages
Very fast simulation time
Can cover all possible faults
Mean Time To Manifest errors to outputs:
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For SRAM-based FPGAs
MTTM(Control/clocking) < MTTM(routing)
MTTM(routing) < MTTM(LUT)
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Appendix & Backup
2004 MAPLD/221
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Background: Soft Error Origin
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The main sources in terrestrial conditions:
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Soft Error occurs:
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Alpha particles & Neutrons
if hitting particles generate more than Qcrit
Critical Charge (Qcrit):
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the minimum charge needed
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To flip the value stored in the cell
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Exp. Increase of Soft Errors
1.00000
0.90000
SRAM: exp(-Qcrit/Qs)
0.80000
Latch: exp(-Qcrit/Qs)
0.70000
0.60000
0.50000
0.40000
0.30000
0.20000
0.10000
0.00000
600 nm
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350 nm
250 nm
180 nm
130 nm
100 nm
70 nm
50 nm
e-Qcrit/Qs trend with technology scaling (Shivakumar , DSN 2002)
• Qcrit: the critical charge (depend on characteristics of the circuit)
• Qs: the charge collection efficiency of a particle strike on the device
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Particles of lower energies occur far more frequently
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Background: Definitions
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How to express Soft Error Rate (SER)
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MTBF (Mean Time Between Failures)
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FIT (Failure-in-Time)
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1 failure in a billion hours
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1 year MTBF = 114,155 FIT
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Background: Definitions
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Failure definition:
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(a) Propagation of an erroneous value
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to at least one flip-flip or primary output
or
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(b) Propagation of an erroneous value
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Definition (a) is compatible with (b)
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to at least one primary output
If there is no redundant flip-flop in the circuit
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Failure Error Rate of LUT
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To reduce number of nodes
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P(tx): the probability of O=tx
LUT failure rate
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LUT as a complex gate
LUT
F1
F2
F3
F4
t0
t1
t2
t3
t4
t5
t6
t7
t8
t9 t10 t11
O
t12 t13 t14 t15
SO=[AP(t0)+AP(t1)+…+AP(t15)].r.NO
= r.NO
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Xilinx Virtex FPGA Model
CLB
Logic block
IO Mux
Switch
Matrix
(SM)
Line
Segments
IOB
2004 MAPLD/221
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CLB Architecture
2004 MAPLD/221
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Error Models in FPGAs (Cont.)
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Config. Bits:
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Care bits
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Don’t care bits
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2004 MAPLD/221
All 1s
Some of 0s
Some of 0s
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Error Models: PIP Short/Open
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10: causes open
01: may cause short or bridging error
1
0
1
0
0
1
0
N2
Stuck-closed: Permanently ON
N1
N3
N3
E1
W1
E1
W2
E2
W2
E2
W3
E3
W3
E3
S2
S1
S3
Stuck-open and stuck-closed errors
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N2
W1
S1
1
Bridiging error
Stuck-open: Permanently OFF
N1
1
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S2
S3
Bridiging error
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Error Models (Cont.)
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Buffer on/off
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1
0
0
1
1
Tri-state buffers
Used in IOBs
Buffer on
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0
Look-Up Table
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Buffer off
F1
0
LUT
1 1
F2
0
1
0
F3
1
1
0
1 O
1
F4 0 1 1
1
1
1
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