Transcript Slide 1

An Architecture for Reconfigurable
Computing in Space
Robert F. Hodson1, Kevin Somervill1, John Williams2, Neil
Bergman2, Rob Jones3
1NASA
LaRC, 2University of Queensland, 3ASRC Aerospace
RSC
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RSC Goals & Objectives
• To develop the next generation high performance spacequalified computing system leveraging…
– Field Programmable Gate Arrays FPGAs
– Intellectual Property (IP)
• Soft cores, processors
– COTS software architectures
• Multi-processor
• Specialized
• Meet Strategic Challenges
– Reconfigurability
– Modularity
• First step towards the next
generation avionics suite
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Why Reconfigurable Computing with Soft Cores & Custom Logic
•
Soft cores readily
available for rad-tolerant
FPGAs
•
Custom co-processors
can improve
performance on average
by 5.8X
•
Power consumption can
also be reduced on
average by 57%
•
Reconfiguration allows
many designs without
hardware redesign –
reducing cost
•
Making this approach
competitive with current
space computing
systems
Source: R. Lysecky and F. Vahid, “A Study of the Speedups and
Competitiveness of FPGA Soft Processor Cores using Dynamic
Hardware/Software Partitioning,” Design Automation and Test in Europe
(DATE), March 2005
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Scalable Architecture
Multiple interconnected general purpose processing nodes with optimized custom
logic attached for special purpose processing.
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Physical Concept
Stacks of reconfigurable processing
modules (RPMs) similar to a
ruggedized version of a PC104+ stack.
Modules, which make up a stack will
be RPMs, Command Control Module
(CCM), Network Module (NM), etc.
Modules
Physical design will support launch
loads, radiation shielding, and
conduction cooling.
STACKS
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Modular Technology
– Allows mixing and matching of
appropriate modules to meet
mission requirements
• Planned modules
Network Module
(NM)
Reconfigurable Processing Module
(RPM)
Reconfigurable Processing Module
(RPM)
– Reconfigurable Processing
Module (RPM)
– Command/Control Module
(CCM)
– Network Module (NM)
– Power Module (PM)
Reconfigurable Processing Module
(RPM)
Command Control Module
(CCM)
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Power Module
(PM)
BUS
• Modules will be combined to
build RSC systems
• Designs will be based on rugged
small form factor modular
stackable technology
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Multiple Interconnected RSC Stacks
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Software Architecture
MPI
uCLinux
RSC plans to deliver a
complete system with
hardware, system software,
development software, and a
demonstration application.
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Reconfigurable Processing Module
RPM
Xilinx FPGA (V4FX60)
Custom
Logic
uB
Config
Memory
(2.5 Gbps)
(512 MB)
SDRAM I/F
NVR I/F
PCI I/F
Serial IO
SDRAM
Bus
NVRAM
(FLASH
or CRAM
32MB min)
SERDES
Switch
SLin
Config Frame Buf
Mgr
Instr
Cache
SLout
Parallel IO
Data
Cache
NIC
Actel FPGA
PCI Bus 33MHz 32/64 Bits
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RPM Features
• Xilinx logic is triplicated and scrubbed
– Custom cache design (MicroBlaze cache not used)
• Caches will be scrubbed
• SDRAM is SECDED protected and scrubbed.
• Rad-Hard NVRAM is an issue
• Compressed code image and configuration is stored in
NVRAM. It is copied to SDRAM and decompressed
after reset.
– If the system has multiple MicroBlaze processors they each
have separate memory space in the same physical memory.
• Custom logic can communicate via FSL or OPB
• PCI interface supports Master/Target/DMA
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Application/MPI
Sockets
message
Transport
UDP
packet
Network
Internet Protocol
IP Address and Size of Datagram
RSC Protocol Stack
Buses
Receiving
CPU or NM
Message
Message
INTR
IP
PHdr
Data
PHdr
Data
IP
DMA Engine
NIC
datagrams
Data Link
and Physical
Sending
CPU
Network Req
Data
PHdr
Data
NIC
INTR
Pull
PCI Address and Size of Datagram
ACK
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PHdr
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Communication Event Sequence
2. Message
send request.
Source NIC
CPU
Controller
Req queue
9. Interrupt to source
CPU. Buffer can now
be released.
Source RPM
3. IP address is
translated to PCI
address of destination.
SDRAM
Message
Buffer
IP2PCI
Mapping
PCI I/F
5. Destination NIC pulls
(DMAs) message into
destination RPM’s memory.
PCI Bus
1. Datagram is built
in memory.
4. PCI Address of
message on
source RPM sent
to destination NIC.
8. Destination NIC tells
source NIC “message
received.”
IP2PCI
Mapping
PCI I/F
Message
Buffer
Controller
Req queue
Destination NIC
CPU
6. Message received
interrupt sent to CPU.
Destination RPM
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SDRAM
7. Message
processed.
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Command & Control Module
The Command and Control
Module (CCM) provides the
primary command interface
to the system. If also
controls the system bus
initialization and boot
process.
CCM
Memory
NVRAM
Discrete IO
Memory
Controller
System
Reset
Reset
Test port
1553 Command I/F
IO
Controller
uController
Configuration and
Code Selects
Hub
Power
Good
Power
Mgmt
PCI Backend I/F
PCI Arbiter
PCI Master/Target
PCI
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Network Module Design
To/from other stacks
SERDES
SERDES
SERDES
SERDES
Link
I/F
Routing Lookup
Additional Link I/Fs
Control
From Link
Interfaces
To Other Link Interfaces
From Link
Interfaces
Routing Lookup
Actel AX2000
PCI
I/F
Control
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DMA
Network Module (NM) provides
an interface to other RSC stacks.
It buffers and routes IP packets
based on routing information
loaded during system
initialization. Serialized links
provide a high-bandwidth
interconnect to other systems.
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RSC Robotic Demonstrator
• Demonstrate reconfigurable
technology on a challenging
real-time control and processing
application
• Tele-operated robot with
multiple sensors
–
–
–
–
–
Stereo camera
Omni camera
IR camera
X-Ray florescence sensor
Several others
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RSC Team
• Core Team Members
– NASA Langley Research
Center (Lead)
– NASA Goddard Space
Flight Center
– The University of
Queensland
– ARSC Aerospace
– Jefferson Lab (DoE)
– Starbridge Systems
– Department of Defense
• Affiliate Members
– Air Force Research
Laboratory
– SEAKR Engineering
– Imagination Engines
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