Transcript Slide 1

CMS Outer Tracker Readout at SLHC
1) some ideas on front end architectures for short strip readout
concentrating mainly on power issues
2) outline of plans for 3 year work program to develop a FE readout chip
Mark Raymond – Imperial College
CMS SLHC tracker, Feb 2007
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CMS LHC tracker FE system
current tracker readout analogue
custom link driver chip at 40 Ms/s
FED digitizes at 10 bits/sample
SLHC will most likely use fast (multi-Gbit/s)
serial digital links
following industrial developments
for digital data transmission
 can only retain analogue info
if low power ADC on front end
CMS SLHC tracker, Feb 2007
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SLHC FE architecture
generic pipeline chip architecture – where to go digital?
FE amp
pipeline
A
pipeline
readout 128:1 mux
B
A) before pipeline
ADC on every channel – power issues
digital multi-bit pipeline
fast FE to achieve single bunch resolution
serial digital O/P
B) after mux
ADC power shared by 128 channels
analog pipeline, analog mux
could keep slow FE + decon pipeline readout
ADC power drives choice of A or B
other possible FE chip features
on-chip sparsification
keep option open - maybe better to do further up the readout chain?
L1 trigger contribution
can short strip layers provide anything useful?
would certainly place significant constraints on FE chip architecture
CMS SLHC tracker, Feb 2007
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ADC power consumption
International Technology Roadmap
for Semiconductors (ITRS-2003)
(forecast from the semiconductor
industry with 15 year perspective)
*
ADC power given by process,
Effective No. Of Bits, and
conversion frequency
based on general considerations
(individual architecture dependent)
90
ADC power @ 20 MHz [mW]
ADC on every FE channel hard to do
130nm
65nm
8bits
6.4
2.5
6bits
1.6
0.6
8 bits @ 20 MHz -> 6.4 mW (0.13mm)
ADC on every FE chip quite possible
6.4/128 -> 50 mW/chan
*from A. Marchioro talk at 2
CMS SLHC tracker, Feb 2007
nd
SLHC workshop
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front end power
how much power can be saved 0.25 -> 0.13?
APV25
can estimate, but learn more by trying to translate circuits
e.g. will show here results for APV preamp/shaper circuit
2.5V
1.25V
have tried to make straightforward translation
but one main difference for preamp
APV25: 3 supply rails (0, 1.25V, 2.5V)
1.25V included to save power
400μA (1.25V), 110 μA (2.5V) = 0.78 mW
propose not to do this again for SLHC
use 2 rails only, 0 and 1.2V, and accept power penalty
1.2V
0.13mm
1.2V
CMS SLHC tracker, Feb 2007
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preamp/shaper design (1)
APV25
Cf
0.13mm
60uA
CL
25uA
50uA
CC
CDET
50uA
25uA
CC
CDET
Cf
Cfs
Cfs
460uA
50uA
CL
100uA
10uA
Preamp
noise & speed depend on input device transconductance (gain) gm
noise  CDET/√gm
gm  COX(W/L)IDS
risetime  CDETCL/Cfgm
IDS
S.I.
W.I.
shorter strips -> smaller CDET so lower gm tolerable
if choose to accept ~ factor 2 increase in noise slope (over APV25) then gm(0.13) = gm(0.25)/4
simulations show this achieved for ~ 100 mA in 0.13 I/P device (W/L = 1000/0.24)
total preamp power (including source follower) = 125 mA x 1.2 V = 0.15 mW
factor ~ 5 reduction from 0.78 mW (APV25 preamp only)
CMS SLHC tracker, Feb 2007
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preamp/shaper design (2)
APV25
Cf
0.13mm
60uA
CL
CDET
25uA
50uA
CC
50uA
25uA
CC
CDET
Cf
Cfs
Cfs
460uA
50uA
CL
100uA
10uA
shaper
0.13 mm architecture identical to APV25, 50 ns time const.
keep gain as high as possible
80 mV/mip c.f. 100 mV/mip for APV25 (1 mip = 4 fC here)
makes best use of available dynamic range, but will only work for one polarity (-ve input signal)
=> need alternative architecture for p-strip signals
total 0.13 mm shaper power 42 mW
factor 6 reduction from 250 mW (APV25)
CMS SLHC tracker, Feb 2007
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0.13 preamp/shaper simulated performance
1.0
pulse shape vs. signal size
1200
1000
ENC [e]
[volts]
0.9
0.8
0.7
0.6
0.98
0.96
1 - 5 mips
ideal 50 ns CR-RC
50 ns/div.
0.90
0.88
600
400
200
0
-5
0
5
10
15
simulated noise slope ~ 70 e/pF => I/P device noise
=> input spectral density ~ 2.6 nV/√Hz, compares
quite well with transistor measurement ~ 2 nV//√Hz
13.5 pF
9 pF
4.5 pF
1.5 pF
0.92
800
Cadded [pF]
pulse shape vs. Cadded
0.94
[volts]
noise vs. Cadded
with pulse shape tuning can cope with strips up to ~ 10 cm
overall preamp/shaper power consumption reduction
1.025 mW (APV25) -> 0.192 mW (0.13 mm)
0.86
factor ~ 5
50 ns/div.
CMS SLHC tracker, Feb 2007
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further up the readout chain
FE chips
slow(ish) digital
serial data
digital link interface functionality
off-detector
multiplexing
sparsification here maybe?
encoding and fast serialization
how many front end chips/ link? (currently 2 APVs/fibre)
depends on output link speed and data volume/FE chip
CMS SLHC tracker, Feb 2007
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some data rate numbers
L1 trigger rate 100 kHz, 10 msec spacing (on average)
APV O/P Frame
current APV data frame duration 7 msec for 140 samples
digital header
digitize at 8 bits -> 1120 bits to shift out in 7 msec = 160 Mbits/sec
• this would be the transmission speed at FE chip output
without sparsification
if 20 FE chips / digital optical link (for example)
128 analogue samples
20 MHz readout -> 7 ms
=> 3.2 Gbits/sec raw data
if front end sparsification (or faster links) then FE chips / link can increase
CMS SLHC tracker, Feb 2007
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3 year work program
proposed SLHC upgrade date 2015 (~ 8 years away)
large scale manufacture of components has to start much sooner
=> need tested solutions ~ 2010/11
outline here a 3 year program to develop a FE chip for short strip readout at SLHC
CMS SLHC tracker, Feb 2007
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3 year FE chip development program
Year 1 (2007 – 8)
develop FE chip specifications (can begin now)
investigate, design and submit solutions for:
different sensor technologies (polarity, strip length, AC/DC coupling, …)
several FE variants to study here
one design to suit all likely to be inefficient (and difficult!)
low power ADC architecture
… not forgetting system issues
choice of powering scheme (serial/parallel)
power supply rejection (DC-DC conversion)
DC balanced digital interfaces (serial powering)
definition of system interfaces (control and readout)
electrical standards, digital protocols, on-chip PLL
physical design of hybrid, module and rod/petal, and manufacturing issues
e.g. sensor/FE chip/hybrid interconnection (bump-bonding?)
CMS SLHC tracker, Feb 2007
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3 year work package for front end (cont’d)
Year 2 (2008 - 9)
extensive testing program
• functionality and performance
• radiation (ionizing and SEE)
review specifications
design and submit ~ complete FE chip prototype
Year 3 (2009 - 10)
more testing
prototype module construction and evaluation
details depend on availability of other components
finalize 0.13 mm chip design
final submission – pre-production circuit
CMS SLHC tracker, Feb 2007
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resources
In UK we are currently preparing bid for funds for SLHC activities
including outer tracker FE chip development
main FE electronics resources required:
funds to participate in 3 MPW runs (0.13 mm)
design effort (RAL)
probably more options to investigate than resources can support
=> either narrow down options
=> or devote more resources – scope for collaboration
CMS SLHC tracker, Feb 2007
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conclusions
FE architecture
on-chip digitization required if want to retain analog info at SLHC
ADC on every channel seems not possible in 0.13 mm
ADC per FE chip (after mux) is possible
slow (50 ns) FE preamp/shaper power can reduce substantially in 0.13 mm technology
still maintaining good S/N for strips up to ~ 10 cm if required
3 year work program
need to establish a funded work program to pursue:
design studies to investigate and define architectures
hardware implementations of most promising candidate architectures
We (CMS-UK) are planning to bid for funds for outer tracker FE chip development
plenty of scope for collaboration
CMS SLHC tracker, Feb 2007
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extra
CMS SLHC tracker, Feb 2007
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APV25 architecture reminder
preamp
inverter
shaper
0.8 mW
0.5 mW
0.25 mW
analogue
pipeline
APSP
differential
analogue
output
128:1 mux
0.2 mW
0.55 mW
(digital ~0.4 mW)
remember existing architecture was also driven by low power
original target 2 mW/chan (~2.8 achieved)
slow 50 ns CR-RC shaping helps with input stage power
but preamp/inverter/shaper power still dominates
implementing deconvolution in APSP pipeline readout circuit
gives single bunch resolution with no extra power
1.2
20 MHz
w1=1, w2=-.74, w3=.14
1.0
0.8
50 ns
CR-RC
0.6
0.4
0.2
0.0
1.2
0
25
50
100
125
150
175
200
0
25
50 ns75/ div100
50
125
150
175
200
1.0
relevance to SLHC?
switchable weights to APSP could allow 20/40 MHz
bunch crossing frequency adaptability without much
extra complexity
0.8
75
40 MHz
w1=1, w2=-1.21, w3=.37
0.6
0.4
0.2
0.0
CMS SLHC tracker, Feb 2007
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Power provision
0.25 mm -> 0.13 mm
chip supply voltages halve, so currents double for same power consumption
=> 2x power dissipated in cables and 2x voltage drop along cables
solution is to deliver power at higher voltage (lower current)
=> local DC-DC conversion or serial powering -> both have implications for FE chip
serial
IIN
parallel
M1
M2
M3
Mn
IOUT
VIN
GND
chain of modules at different DC voltages
linear regulation on each module
AC or opto-coupling of signals (readout & cntrl)
DC-DC
conversion
M1
M2
M3
Mn
module powering more conventional
DC-DC conversion the main issue
FE chip supply rejection issues?
see DC to DC Power Conversion, Ely and Garcia-Sciveres, LECC 2006 (Valencia)
CMS SLHC tracker, Feb 2007
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0.13 mm input transistor choice
0.13 mm gm vs. W (L=0.12,0.24,0.36,0.48)
input device choice determined by:
10
ID=400uA
O/P risetime goes as CDET/gm
goes as CDET/√gm
8
gm [mA/V]
speed:
thermal noise:
CDET  strip length so lower gm possible
allowable bias currents put 0.13 μm devices in W.I.
6
ID=200uA
4
ID=100uA
gm  ID with very weak W/L dependence
2
0
rigorous (complicated) optimisation required (including power)
0
200
400
600
800
W [um]
1000
1200
1400
1600
make some simple choices here
lets say CDET reduces factor 4, => gm can also reduce factor 4 (so noise slope increases factor 2)
choose W/L = 1000/0.24 here and ID = 100μA,
-> gm > 2 mA/V
CMS SLHC tracker, Feb 2007
(APV25 I/P device gm ~ 8 mA/V)
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50/25 nsec
50/25 ns pulse shapes for different CDET values
is 25 nsec pulse shape possible without changing
shaper transistor dimensions?
0.96
yes - can speed up pulse shape using Isha/vfs only
0.94
but power penalty
0.92
0.90
0.88
0
100
200
300
400
CDET
isha(50ns) P[mW]
isha(25ns) P[mW]
0
4.5
9
13.5
10
10
12
14
20
25
35
50
12
12
15
17
24
30
42
60
500
-9
x10
CMS SLHC tracker, Feb 2007
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50/25ns simulated noise performance
ENC vs, Cadded
1400
1200
50 nsec shaping
160 + 70/pF
ENC [e]
1000
25 nsec shaping
200 + 90/pF
800
600
400
200
0
-5
0
5
10
15
Cadded
CMS SLHC tracker, Feb 2007
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straw man detector module designs
Sandro
Geoff
Present CMS Si-strip tracker modules come in many different variants
different sensor pitches/shapes, different #’s of FE chips/ module, different mechanical designs
What will SLHC Si-strip modules eventually look like?
don’t know, but things to consider are how much can be sacrificed for manufacturability
bump-bonding is one common theme in above examples
Choices here will affect final FE chip design (but maybe not crucial to know the answers now)
CMS SLHC tracker, Feb 2007
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W/L = 1000/0.24 noise spectral density
measurement
*
2 nV/√Hz @ 100 mA
* from Manghisoni et al, Noise performance of 0.13mm Technologies for detector front-end applications
IEEE Trans.Nucl.Sci. Vol.53, no.4,Aug.2006 (2456-2462)
CMS SLHC tracker, Feb 2007
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