Transcript Slide 1

Nanoscale Silicon Technology
Presenters
Topics
Mike Duffy
Double-gate CMOS
Eric Dattoli
Strained Silicon
Alain Espinosa
Thin Gate Insulators
Challenges as CMOS
feature sizes decrease
1. Carrier Mobility reduction
2. Threshold voltage (VT) control reduction
3. Off-state leakage increase
4. Power consumption increase
A basic MOSFET:
Band diagram
when on:
Eeff
Problem 1: Carrier Mobility Decreases as Channel
length decrease and Vertical Electric fields increase
Mobility versus technology scaling trend for Intel process
technologies. From (Thompson 2004)
Problem 2: VT Rolloff as Channel length decreases
Substrate-Strained Silicon Technology: Process Integration
H. C.-H. Wang, IEDM 2003
One common solution : Increasing Channel Doping reduces Short
Channel Effect
(Problem 2) VT Rolloff explained by
Short Channel Effect
This problem is addressed by Double Gate Technology
Problem 3: Tunneling Through Gate Oxide
(off state current)
Eox
This problem is addressed by Strained Silicon, and
Thin-Insulator technology
Problem 4: Wattage/Area increases as density increases
MOSFET Scaling Trends, Challenges, and Potential Solutions Peter M. Zeitzoff and James
E. Chung. IEEE CIRCUITS & DEVICES MAGAZINE ¦ JANUARY/FEBRUARY 2005
This problem is addressed by Double Gates, Straining,
and thin Gate Insulators
Double Gate MOSFET
Features:
• Upper and lower gates control the channel region
• Ultra-thin body acts as a rectangular quantum well at device limits
• Directly scalable down to 20 nm channel length
Band Structure
Layout
• Type I : Planar Double Gate
• Type II: Vertical Double Gate
• Type III: Horizontal Double Gate (FinFET)
FinFET Layout
Reduced Channel and Gate Leakage
• Short channel effects are seen in Standard silicon MOS devices
• DGFET offers greater control of the channel because of the double gate
• Gate leakage current is prevented by a thick gate oxide
Threshold Voltage Control
Silicon MOS Transistor:
• Increased body doping used to control VT for short channel
• Small number of dopant atoms for very short channel
• Lowest VT achievable is .5V
Double Gate FET :
• Increased body doping
• Asymmetric gate work functions (n+ / p+ gates)
• Metal gate
• VT of .1V achievable through work function engineering
Increased Carrier Mobility
Silicon MOS Transistor:
• Carrier scattering from increased body doping
• Transverse electric fields from the source and drain reduce mobility
Double Gate FET:
• Lightly doped channel in a DGFET results in a negligible depletion charge
• Asymmetric gate: experiences some transverse electric fields
• Metal gate: transverse electric field negligible with increased channel control
Reduced Power Consumption
• Double Gate coupling allows for higher drive currents at lower supply
voltage and threshold voltage
• Energy is a quadratic function of supply voltage
• Reduced channel and gate leakage currents in off state translate to huge
power savings
• Separate control of each gate allows dynamic control of VT :
Simplified logic gates would save power and chip area
Power VS Feature Size
Challenges Facing Double Gate Technology
1) Identically sized gates
2) Self-alignment of source and drain to both gates
3) Alignment of both gates to each other
4) Connecting two gates with a low-resistance path
Ultimate Double Gate Limits
1) Thermionic emission above the channel potential barrier:
Short channel effects lower potential barrier
2) Band-to-band tunneling between body and drain pn junction:
Body-drain electric field increases tunneling probability
3) Quantum mechanical tunneling directly between source and drain:
Extremely small channel lengths correspond to narrow
potential barrier width
4) Other effects of quantum confinement in the thin body
Si/Ge Alloys
Lattice Constants:
Si
5.431 Angstrom
Ge
5.658 Angstrom
Alloys are uniform crystal structures containing two different
materials which posess the same ordering property.
Can create Si1-xGex alloys where x is a number from 0.0 to 1.0
This is possible since both materials create diamond type lattices
and their lattice constants are close.
Lattice constant of alloy is determined by Vegard’s Law, which is a
linear average between the constants of Si and Ge.
aalloy = (1-x) • aSi + x • aGe
Note: other material parameters change: e.g. bandgap
Deviation from Vegard’s Law (Herzog 1993)
Si and Si1-xGex Alloy Heterostructures
A Heterostructure is a semiconductor structure in which the material
composition changes with position. Heterostructure devices are made
by using Molecular Beam Epitaxy to grow a different material on a substrate.
Performance Projections of Scaled CMOS Devices and Circuits With Strained Si-on-SiGe
Channels. Jerry G. Fossum, Fellow, IEEE TRANSACTIONS ON ELECTRON DEVICES,
VOL. 50, NO. 4, APRIL 2003
Si
Ge
Si
Ge
Physics of Semiconductors and their Heterostructures. Jasprit Singh
Solid State Electronic Devices. Streetman
Required to lay heterolayer within a
constrained thickness
Substrate-Strained Silicon Technology: Process Integration
H. C.-H. Wang, IEDM 2003
Scale Picture of Strained Si NMOS Heterostructure
Improved Hot-Electron Reliability in Strained-Si nMOS
David Onsongo, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO.
12, DECEMBER 2004 2193
Strain Engineering
X
Y
Z
Process-Strained Si (PSS)
CMOS Technology Featuring
3D Strain Engineering
C.-H. Ge, IEDM 2003
<100> Strained-SiGe-Channel pMOSFET with Enhanced Hole Mobility
and Lower Parasitic Resistance
v Masashi Shima FUJITSU Sci. Tech. 2003
<100> Orientated Wafer
Biaxial tension in Strained Si on SiGe MOSFET
Fabrication and Analysis of Deep Submicron Strained-Si N-MOSFET’s
Kern (Ken) Rim, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO.
7, JULY 2000
.19 m0 < .98 m0
LH
HH
Scaling Planar Circuits
IEEE Circuits & Device Magazines Jan/Feb 2004
Z
Rim (2000)
X
Carriers in channel
travel along X-Y plane
in k-space
Y
Carriers move along [010] or
[100] direction
Applies to common (001) oriented
Silicon substrate
Same Z or [001] Axis in Real Space
Relationship between effective mass and
carrier mobility
Carrier mobility is given by:
μn= q • t
mn*
Current Density depends on Carrier mobility:
Jx = q • n • μn • εx
This decrease in carrier mobility is addressed by
Strained Silicon. Specifically, we’ll see that mn*
is reduced
Bonus: Tunneling through Gate Oxide decreases
with Strained Silicon
Channel Structure Design, Fabrication and Carrier
Transport Properties
of Strained-SYSiGe-On-Insulator (Strained-SOI) MOSFETs
S. Takagi+
IEDM 2003
Problem To Solve:
We will use the WKB Approximation to
calculate how much the Gate Tunneling
Current is reduced by increasing the
insulator/channel barrier height.
Remember, Straining increases the
insulator/channel barrier height.
Transmission Probability depends on meff,
Electric Field across barrier(Eox) ,and barrier
height (Φox)
How To Find Si/SiO2 Barrier Height and Eox of
Triangular Barrier
Eox
Unstrained:
Φox=3.2 eV
Strained:
Φox=3.3 eV
Device Design for Sub-0.1µm MOSFETs for Sample and Hold Circuits. 2003 Mayank Kumar Gupta
Compare 5x difference in Gate Current to difference in
Jg (gate current density) at Eox = 8 MV/cm
1/(8 MV/cm) = 0.125
ln (J unstrained) = -12.9
ln (J strained) = -14.6
Their difference is exp(1.7) =
5.5
Which is very close to the
theoretical result of 4.7x from
the WKB Approximation. This
difference isn’t constant, at:
• Eox = 7.4 MV/cm, there is about a 7.5x difference
• Eox = 9.1 MV/cm, there is about a 4.5x difference
Difference in Junstrained/Jstrained as Eox varies is
predicted by the theoretical WKB approximation
Compares to
experimental
difference of 4.5x
Compares to
experimental
difference of 7.5x
Effects of Eox on Tunneling Current through Gate
Improved Hot-Electron Reliability in Strained-Si nMOS
David Onsongo, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO.
12, DECEMBER 2004 2193
Better Way to Engineer Strain
A 90-nm Logic Technology Featuring Strained-Silicon Scott E. Thompson, IEEE
TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 11, NOVEMBER 2004
Strain Applied to NMOSFETs
MOSFET Current Drive Optimization Using Silicon Nitride
Capping Layer for 65-nm Technology Node. S. Pidin 2004
Symposium on VLSI Tech Digest
Advantage over Si on SiGe method
This method improves Drain Currents for:
NMOS
PMOS
A 90nm High Volume Manufacturing Logic Technology Featuring
Novel 45nm Gate Length Strained Silicon CMOS Transistors. IEDM 2003
SiO2 limitations
• Scaling
• Power Consumption
• One solution is using High-k dielectric
material
High-k dielectric material
• Are used to minimize tunneling current
and the out diffusion of boron from the
gate.
• Types
1) 4 < k < 10 ; SiNx
2) 10 < k < 100; Ta2O5, Al2O3, TiO2
3) 100 < k
• What we are looking for in High-k dielectrics?
One Example of High-k dielectrics
• Al2O3
• I-V Plot for different thicknesses on Si(100)
Al2O3 continued
• Dielectric Constant (k)
• Recent study show Al2O3 tunneling
dielectrics <1nm thick are superior to
previously used Si3N4 and SiO2
Some recent of High-k dielectrics
• Al2O3 film have been used to make
1Gbit DRAM
• Al2O3 and HfO2 have been used to produce
a Vertical Replacement-gate (VRG) n-Mos.
-Conclusions on High-k dielectrics
Thank you
Questions?
Side Problem: Increasing Channel Doping
decreases mobility
Solid State Electronic Devices. Streetman