Transcript FEE2016_ALPIDE_TK_v1x

10th International Meeting on Front-End Electronics (FEE 2016)
Krakow
01/06/2016
Thanushan Kugathasan, CERN
on behalf of the ALICE collaboration
ALICE Inner Tracking System Upgrade
ALICE detector at LHC, CERN
Objectives
Improve impact parameter resolution by a factor of
3 (5) in r–φ (z) at pT = 500 MeV/c
Get closer to IP (radius of first layer):
39 mm -> 23 mm
Reduce pixel size:
50 mm x 425 mm -> O(30 mm x 30 mm)
Reduce x/X0/layer:
~1.14% -> ~0.3% (inner layers)
Better tracking efficiency and pT resolution at low pT
Finer granularity:
from 6 to 7 layers and all layers with pixels
Fast readout
Technical Design Report for the Upgrade
of the ALICE Inner Tracking System
J. Phys. G 41 (2014) 087002
CERN-LHCC-2013-024 ; ALICE-TDR-017
Readout Pb-Pb interactions at 100 kHz
Readout pp interactions at >200 kHz
(current ITS limited at 1 kHz)
Design for fast removal and insertion
Maintenance during yearly shutdown
Installation of the new ITS during LHC Long Shutdown 2 (2019 - 2020)
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New ALICE ITS layout
Outer
Barrel
Inner
Barrel
~24000 CMOS Pixel Sensors
10 m2 sensitive area
12.5 Gpixels
Coverage
23 mm < r < 400 mm, |h| < 1.22
Layers z-lengths: 27 - 150 cm
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ITS Chip General Requirements
Parameter
Inner Barrel
Chip size (mm x mm)
Outer Barrel
15 x 30
Chip thickness (mm)
50
100
Spatial resolution (mm)
5
10 (5)
Detection efficiency
Fake hit rate
> 99%
< 10-5 evt-1 pixel-1 (ALPIDE << 10-5)
< 30
Integration time (ms)
Power density (mW/cm2)
TID radiation hardness (krad) (**)
NIEL radiation hardness (1 MeV neq/cm2) (**)
< 300 (~35)
< 100 (~20)
2700
100
1.7 x 1013
1.7 x 1012
Readout rate, Pb-Pb interactions (kHz)
Hit Density, Pb-Pb interactions (cm-2)
(< 10)
100
18.6
2.8
(*) In
color: ALPIDE performance figure where better than requirements
(**) 10x radiation load integrated over approved program (~ 6 years of operation)
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Technology
•
TowerJazz 180 nm CMOS imaging process
•
Gate oxide 3 nm thick, good for TID tolerance
•
High-resistivity (> 1kW cm) p-type epitaxial layer (18 µm to 30 µm) on p-type substrate
•
Deep PWELL shielding NWELL allowing in-pixel PMOS: circuits beyond rolling shutter
NWELL
PMOS
NMOS
TRANSISTOR TRANSISTOR
Spacing DIODE Spacing
p+
n+
pwell
deep pwell
p+
p+
p+
nwell
n+
n+
n+
p+
pwell
nwell
deep pwell
Collection
diode
h
e
Depletion
region
•
•
•
e
h
h
e
h
Substrate reverse bias to increase depletion
volume around the collection electrode
e
p-- epitaxial layer
Better tolerance to non-ionizing radiation
Lower input capacitance Cin
Smaller cluster => more charge Q in the
central pixel
p substrate
Particle hit
High Q/Cin allows for a lower power circuit for a
given S/N (Signal over Noise) for a given bandwidth
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ALPIDE Architecture
1024 pixel columns
AMP
COMP
Readout (zero suppression)
Readout (zero suppression)
Readout (zero suppression)
Readout (zero suppression)
512 rows
THR
In pixel:
Amplification
Discrimination
3 hit storage registers (MEB)
In matrix:
Zero suppression readout based on
priority encoding:
sequential readout of hit pixels address
Bias, Readout, Control
No free running clock over matrix. No activity if there are no hits
=> power and system noise reduction
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In pixel hit discrimination and storage
Cdet~2.5 fF @ -6 Vbb
Cin~1.6 fF
•
Analog front-end continuously active, acts as an analogue delay line (~2 µs peaking time)
•
Global threshold for discrimination => binary pulse OUT_D
•
Digital in-pixel circuitry with three hit storage registers (multi event buffer)
•
Global shutter (STROBE) latches the discriminated hits in next available register
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Sensor configuration and reset
Diode reset
PMOS reset
PIX_IN
VRESET_D
IRESET
PIX_IN
A)
VRESET_P
A)
p+
p+
pwell
n+
p+
p+
nwell
deep pwell
p+
n+
p+
nwell
pwell
deep pwell
deep pwell
n+
p+
p--
p+
n+
p--
p+
n+
p substrate
C)
B)
Spacing Diameter Spacing
C)
Diode Reset
VRESET_D
p+
p+
p-- epitaxial layer
Collection
diode
D0
p+
p--
n+
p--
VRESET_P
B)
p+
nwell
p substrate
Spacing Diameter Spacing
p+
deep pwell
p-- epitaxial layer
Collection
diode
p+
nwell
PMOS Reset
M0b
p+
PIX_IN
Collection
Diode
SUB
PIX_IN
IRESET
AVSS
Collection
Diode
SUB
• Sensor NWELL collection electrode
• Octagonal shape with 2 μm diameter
• Spacing between NWELL and PWELL : 3 μm (spacing vs circuit area trade-off)
• Reset mechanism
• Diode reset : p+ in NWELL, Reset current depends on the sensor leakage and signal amplitude
• PMOS reset :
• Reset current limited by IRESET (> leakage)  control on the reset circuit conductance
• Additional capacitance on node PIX_IN
ALPIDE implements diode reset
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Front-end operation principle
VDDA
IBIAS
DVsource = DVPIX _ IN
source
DVPIX _ IN
Q
= IN
CIN
PIX_IN
VCASP
Csource
M1
Transfer of charge from Csource to
COUT_A to generate voltage gain
M2
OUT_A
IBIAS
COUT_A
GNDA
•
•
•
Signal charge creates negative voltage step ΔVPIX_IN at the input (PIX_IN)
M1 with current source from VDDA acts as a follower and forces source to follow gate.
This causes transfer of charge Qsource = Csource*ΔVPIX_IN from Csource to COUT_A
•
Ideally:
•
Voltage gain is obtained if:
Csource >> COUT _ A
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Front-end circuit - 1
•
In practice need feedback (to curfeed)
•
•
•
curfeed net : To set M3 gate voltage level to allow IBIAS+ITHR current
ITHR, VCASN : To define the OUT_A baseline voltage level below where IM8 = IDB
ITHR defines the return to baseline of OUT_A after hit
•
Active low output (OUT_D) : M8 current (defined by OUT_A) > IDB
•
The front-end works in weak inversion to reduce power consumption
•
IBIAS = 20 nA, ITHR = 0.5 nA  ~40 nW (1.8 V supply voltage )
Cascode transistors to avoid Miller effect on parasitic
capacitances between high gain nodes
•
M2 for : PIX_IN to OUT_A
•
M9 for : OUT_A to OUT_D
Reverse bias feature
PMOS current bias only
no sensitivity to reverse bias
NMOS transistors bulk bias change Vth
bias correction needed
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Front-end circuit - 2
< OUT_A >
20nA
4.5 nA
Input charge
0.5nA
Clipping point
( OUT_A - curfeed > Vth M6)
Threshold of second stage
( IDB = IM8 )
Charge Threshold
OUT_A base line
< OUT_D >
•
Combined capacitance to reduce layout area
•
•
Charge threshold parameters
•
•
•
Csource and Ccurfeed  Cs
OUT_A baseline value : ITHR,VCASN
Threshold of second stage : IDB
Clipping transistor M6
•
•
Input charge
dvOUT _ D
IDB
=
dt
COUT _ D
Large input pulse compression
VCLIP to tune the clipping point
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Front-end layout
Area ~ 220 μm2
26.8 μm
Cs
M0
10 μm
Cs
M4
M5
M2
M3
M8
M6
M1
M7
Cs
M9
14 μm
3 μm Device size limited by layout area.
Pixel logic
Device size limited by load capacitance
12.8 μm
Device sizing optimized to improve charge threshold and pulse duration uniformity
First stage input PMOS (M1): trade-off on input capacitance vs RTS noise
option (a): W = 0.22 µm, L = 0.18 µm (minimum size)
option (b): W = 0.92 µm, L = 0.18 µm (~ 4 times minimum width)
Second stage input NMOS (M8): trade-off on COUT_A and uniformity
Simulation: limited accuracy of transistor capacitance values in weak inversion
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Front-end pulse duration
•
In trigger mode the front-end is used as analogue memory:
• hit information kept up to STROBE arrival
Clipping point
7 μs
•
•
< OUT_D >
Charge
6 μs
threshold
t1 : time walk
t2 – t1 : pulse duration window
t2
: trailing edge of OUT_D
5 μs
4 μs
x
t2 [us]
50 e-
2.9 ±0.20
3.9 ±0.52
100 e-
1.5 ±0.16
5.9 ±0.24
150 e-
0.9 ±0.03
5.7 ±0.09
5 ke-
0.5 ±0.01
2.6 ±0.07
3.0 μs  max. t1
Required STROBE window
x
2 μs
1 μs
t1
: leading edge of OUT_D
50
t1 [us]
Saturation
Pulse duration window
3 μs
Qin
100
150
200
250
300
. . . 5000
< STROBE >
Delay
t
2.6 μs  min.t2
( required max. delay )
Qin [e-]
•
The signal is latched only when both STROBE and OUT_D are active at the same time.
• STROBE window can be defined to latch all charges above threshold:
• STROBE delay has to be larger than the trigger latency (1.6 μs)
• Pulse timing rms variations have to be taken into account (error bars at 5 sigma)
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Pixel matrix
Pixel layout
Collection diode
• 2 µm nwell width
• nwell-pwell spacing 3 µm
Pixel matrix layout
Electrode
26.80 μm
Priority encoder
Priority encoder
Pixel double column
Front end
Pixel Logic:
3 pixel state registers
2 Configuration bits:
Pixel pulsing
Pixel masking
Priority encoder
19.58 μm
29.24 μm
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ALPIDE chip
30 mm
Matrix sensitive area
(512 × 1024 pixels)
< The first full scale prototype : ALPIDE-1 >
Soldering pads
Analog DACs
512 x 26.88 um = 13.76 mm
15 mm
1024 x 29.24 um = 29941.76 um
Digital Periphery
1.208 mm
Regular Pads + Custom Blocks: LVDS, MLVDS, CMOS I/O, Bandgap, monitoring ADC
Sensitive area (4.12 cm2) power density 6.2 mW/cm2
Chip power density < 35 mW/cm2 (20 mW/cm2 with readout from parallel port)
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Full scale prototype characterization



Since end 2011, 4 MPWs and 5 engineering runs.
Small scale prototypes for sensor optimization
Full scale ALPIDE prototypes (1024 x 512 pixels)
 pALPIDE-3 (back from foundry in October 2015)
55Fe
Radioactive source
15 mm
30 mm
8 sectors with different sensor design and front-end options
128 columns/sector
512 rows/column
width 3.74 mm/sector
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Threshold and noise distribution
Charge threshold
Noise
• Results from test charge injection (nominal setting, substrate bias = 0 V)
• Error function (S-Curve) fit :
• Charge threshold : (67 ± 14) e• Noise : (4.1 ± 1.2) e-
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Test beam: input transistor size vs RTS noise
First stage input PMOS (M1):
pALPIDE-3a): W = 0.22 µm, L = 0.18 µm (minimum size)
pALPIDE-3b): W = 0.92 µm, L = 0.18 µm (~ 4 times minimum width)
Same noise level from test charge injection but different fake hit rate => RTS noise
Larger input transistor size reduces significantly RTS noise
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Test beam: effect of reverse bias and spacing
Larger reverse bias and spacing increases detection efficiency
(larger depletion volume)
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Test beam: Resolution and Cluster size
Resolution of 5 µm achieved
Cluster size: between 2 and 3 pixels
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Test beam: TID effect
Performance up to specifications, ionizing radiation 312 krad
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Test beam: NIEL effect
Performance up to specifications, non ionizing radiation 1.7 x 1013 1 MeV neq/cm2
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Conclusions
ALPIDE chip is the CMOS Pixel Sensor that will equip the new ALICE ITS
15 mm × 30 mm, 512 × 1024 pixels, 29 µm x 27 µm pitch
Sensor design optimized for Q/Cin:
diode reset, 3 µm collection NWELL to PWELL spacing
Possibility to apply reverse bias:
further capacitance reduction and non-ionizing radiation tolerance increase
Ultra-low power front-end (40 nW/pixel, 2 µs peaking time).
In pixel discrimination and zero suppressed read-out
Sensitive area (4.12 cm2) power density 6.2 mW/cm2 (full chip < 35 mW/cm2)
Full scale prototype performance up to specifications in test beams with large
operation margin
ALPIDE final design submitted in May 2016
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Backup
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IN-PIXEL PULSING
 Description of injection capacitance and layout
Metal4
1.28μm
0.64μm
Metal3
1.54μm
0.64μm
Pulsing capacitor (0.23 fF) cross section
VPULSE
IN
(M4)
(M3)
(M2)
(M1)
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FRONT END OPTIMIZATION: parasitic components
< Sensitivity of the Charge threshold on CP1 >
Extracted CP1 value : 0.38 fF  25% variation : 0.1 fF
80
VDDA
79
78
IBIAS
IDB
M0
source
ITHR
M4
M7
77
OUT_D
76
Cs
PIX_IN
M1
VCASN2
VCASN
CP0
M5
VCASP
M6
M2
M9
CP1
M8
M3
curfeed
OUT_A
75
Without cascode [M9]
𝒅 𝑸𝒕𝒉𝒓
𝟐. 𝟐 𝒆−
=
𝒅 𝑪𝑷𝟏
𝟎. 𝟏 𝒇𝑭
74
With cascode [M9]
73
𝒅 𝑸𝒕𝒉𝒓
𝟎. 𝟔 𝒆−
=
𝒅 𝑪𝑷𝟏
𝟎. 𝟏 𝒇𝑭
72
71
70
GNDA
0.30
0.31
0.32
0.33
0.34
0.35
0.36
0.37
0.38
0.39
0.40
0.41
0.42
0.43
0.44
0.45
0.46
0.47
0.48
0.49
0.50
•
Parasitic components impact threshold, to mitigate use cascode to reduce Miller effect
• Variation of parasitic capacitance amplified by miller effect
Effect of CP1 mismatch variation on Qthr reduced by factor 4
( rms from transistor : 1.7 e- < without cascode : 2.2e- )
Qthr [e-]
•
CP1 [fF]
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FRONT END OPTIMIZATION: Device sizing
From Monte Carlo simulation optimize device sizing according to influence on charge threshold
26.8 μm
VDDA
μm2
~ 220
IBIAS
source
10 μm
M6
M1
M5
M7
Cs
VCASP
3 μm
M1
12.8 μm
M9
M6
M2
M9
M8
VCASN2
VCASN
M3
OUT_D
Cs
PIX_IN
M5
M2
M7
ITHR
M4
Cs
M4
IDB
M0
Cs
M0
M8
14 μm
OUT_A
curfeed
M3
Pixel logic
Device size limited by layout area.
Device size limited by load capacitance
*rms0 [e-]
W/L [μm/μm]
Area [μm2]
rms [e-]
2.70
1.8/8.5
15.3
0.69
𝟗
𝑨𝒕𝒐𝒕 =
GNDA
𝑨𝒊
 Total area fixed
𝒊=𝟎
M0
M1
0.06
0.92/0.18
0.16
0.14
M2
0.03
0.22/0.18
0.04
0.14
M3
0.22
0.5/5
2.5
0.14
𝒓𝒎𝒔 =
𝒓𝒎𝒔𝟎
𝑨𝑹𝑬𝑨
 rms0 depends on circuit
 Large area required
*rms0 : normalized mismatch value for 1 μm2 transistor area
𝟗
𝒓𝒎𝒔𝒕𝒐𝒕 =
(𝒓𝒎𝒔𝟎𝒊 )𝟐
𝑨𝒊
 Weighted sum of squares
 Area distribution is important
M4
4.63
2/8.4
16.8
1.13
M5
0.92
0.5/10
5
0.41
M6
0.17
0.5/3
1.5
0.14
M7
0.34
0.42/7
2.94
0.2
Version
Qthr [e-]
rms [e-]
Qthr [e-]
rms [e-]
M8
0.58
0.22/4
0.88
0.62
pALPIDE-3
78
1.7
92
2.0
M9
0.04
0.42/0.2
0.08
0.14
Cs
0.91
Cap. : 344 fF
43.09
0.14
𝒊=𝟎
Schematic
Post-layout
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FRONT END: Pulse duration uniformity
Important as front end is used as analog memory
dvOUT _ A I Discharge
=
= ITHR + I M 6
dt
COUT _ A
(before_ clipping _ I M 6 = 0)
Clipping point
OUT_A
•
Wide M4 to reduce ITHR variation
•
Long M6 (clipping transistor) to reduce the clipping point variation
•
Cascode transistor[M9] to reduce COUT_A variation (Miller Effect)
OUT_D
•
Wide M7 to reduce IDB variation
IDB
M0
Clipping
A)
M7
ITHR
M4
OUT_D
Cs
PIX_IN
M1
COUT_D
VCASN2
VCASN
M6
M5
dvOUT _ D
IDB
=
dt
COUT _ D
M8
M3
curfeed
M6
VCLIP
M9
M6
M2
OUT_A
COUT_A
OUT_A
VCASP
B)
OUT_A
source
curfeed
IBIAS
curfeed
VDDA
GNDA
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Pixel logic schematic
Signals buffered from the periphery
2 Configuration bits:
Pixel pulsing
Pixel masking
Charge injection
pulse
Front-end binary output
Output to priority
encoder
Input from priority encoder
3 Pixel State registers
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8 different sectors for pALPIDE-3
VPULSE_*
VRESET_P
AVDD
Cinj
160 aF
M0
M0b
M0a
D0
M7
M4
source
Clipping
IDB
ITHR
IBIAS
HIT_PIX_B
curfeed
Diode Reset
VRESET_D
curfeed
PMOS Reset
pix_in
VCASN2
D1
M5
VCASP
M2
AVSS
pix_out
PWELL
M8
M3
M6
M9
M6
VCLIP
pix_out
VCASN
pix_out
Cs
M1
IRESET
curfeed
8 sectors
128 columns/sector
512 rows/column
width 3.74 mm/sector
AVSS
Sector
M3, M5, M6, M8
VCASN2 (M9)
Clipping M6 gate
M1 bulk
Reset
Spacing
0
optimized size
Yes
diode conn.
AVDD
Diode
2 μm
1
optimized size
No
diode conn.
AVDD
Diode
2 μm
2
as in pALPIDE-1/2
No
diode conn.
AVDD
Diode
2 μm
3
optimized size
Yes
VCLIP
AVDD
Diode
2 μm
4
optimized size
Yes
VCLIP
Source
Diode
2 μm
5
optimized size
Yes
VCLIP
Source
Diode
3 μm
6
as in pALPIDE-1/2
No
diode conn.
AVDD
PMOS
2 μm
7
optimized size
Yes
VCLIP
AVDD
PMOS
2 μm
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Pulse shape
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ToT vs ITHR
Default parameters for Vbb = 0V, sector 5,
pixel 5/5
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VCLIP on ToT
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Threshold and Noise vs ITHR
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RTS noise, pALPIDE-2

Wmin Input transistor (Sector 0 ) vs. ~ 4 * Wmin Input transistor (Sector 1 )

Detection efficiency > 99% ( specification ) for both Sectors

Low threshold setting: Comparable noise level (Gaussian noise)

Nominal threshold setting:

Sector 1 has lower fake hit rate (lower RTS noise)
Sec.
W M1
[μm]
QTHR
[ e- ]
𝝈QTHR
[ e- ]
ENC
[ e- ]
0
0.22
169
13
1.8
1
0.92
150
9
1.7
< Hit map –random triggers >
< Fake hit rate vs ITHR >
Sector 0
Sector 1
Nominal threshold setting ITHR = 500 pA
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