Temperature Safety System for M0` Module

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Transcript Temperature Safety System for M0` Module

Temperature Safety System (TSS)
for the ECAL M0’
Predrag Milenovic, CMS Belgrade Group
• System design and implementation
• Test-beam objectives for TSS of M0’
• Results and Conclusions
CERN, 20. 09. 2002.
CMS Belgrade Group
M0’ TSS Objectives
• Implement Temperature Safety System for M0’:
– Independent and continuous monitoring and archiving of the system
status and temperature of M0’ VFE environment (10 AD590 sensors);
– Reliable hardwire interlocks with High Voltage (HV) and Low Voltage
(LV) Power Supply systems;
– Instant reaction on any critical change of temperature or external
alarms (from the Cooling System) by issuing a proper signal to:
• LV System (hardwired interlock),
• HV System (hardwired interlock ),
• System Operator (soft PVSS Warning and Alarm);
– Robustness and reliability;
• Design and test solutions relevant for the final ECAL TSS:
– PVSS Project for Control and Monitoring of TSS
– PLC Interrupt Routines and OPC connection to TSS Control PC
– PLC performance and time-multiplexing limit.
CERN, 20. 09. 2002.
CMS Belgrade Group
Implementation of the System
CERN, 20. 09. 2002.
CMS Belgrade Group
PVSS Monitoring Panel for M0’ TSS
CERN, 20. 09. 2002.
CMS Belgrade Group
Results and Conclusions (1)
• Developed and successfully implemented software solution for
TSS easily extendable to large number of sensors:
– PVSS Project for Control and Monitoring of ECAL TSS
– Code for PLC Interrupt Routines
• Tested PLC performance:
– Time-multiplexing limit found to be 40ms (A/D conversion time +
integration time ~ 25ms)
– No problem observed with SIMATIC Software
• Occasional problems with PVSS observed during the M0’ run:
– Archiving problem – latest PVSS Patch installed and problem
removed
– PVSS crushes occasionally – problem reduced, but not solved
– Trending tool stops responding occasionally – restart solves the
problem
CERN, 20. 09. 2002.
CMS Belgrade Group
Results and Conclusions (2)
• Alarm logic and Interlocks proved to turn LV and HV off properly
with programmable LV-to-HV time-delay (set to be 40s). Interlock
signals generated and sent in two occasions:
– On 30.07.2002 due to problematic noise in readout system,
– On 05.10.2002 due to power cut of the cooling system.
• Strong influence of H4 environment noise to sensor readout.
Suspected cause: the usage of flat unshielded cable and/or
unshielded PLC rack
• Noise in the HV interlock cable found to be negligible (noise
amplitude ~30mV)
• More detailed studies and analysis of the system behavior should
follow.
CERN, 20. 09. 2002.
CMS Belgrade Group