Transcript Hardware Design Fundamentals for MCU

ID A11C: Hardware Design Fundamentals for
MCU-based Embedded Systems
Renesas Electronics America Inc.
Mitch Ferguson
Manager, Application Engineering
12 October 2010
14 October 2010
© 2010 Renesas Electronics America Inc. All rights reserved.
Version 1.0
Mr. Mitch Ferguson
 Applications Engineer Manager
 Specializes support design teams develop low-noise
systems using MCUs.
 Over 15 years of system-level design experience
 Over 7 years of experience as an application engineer.
 As a hardware engineer and engineering manager, he has
been involved in design in power distribution controls,
automotive and fire alarm systems with focus on EMI/EMS
issues.
 Bachelor of science in electrical engineering from Cleveland
State University
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Renesas Technology and Solution Portfolio
Microcontrollers
& Microprocessors
#1 Market share
worldwide *
ASIC, ASSP
& Memory
Advanced and
proven technologies
Solutions
for
Innovation
Analog and
Power Devices
#1 Market share
in low-voltage
MOSFET**
* MCU: 31% revenue
basis from Gartner
"Semiconductor
Applications Worldwide
Annual Market Share:
Database" 25
March 2010
** Power MOSFET: 17.1%
on unit basis from
Marketing Eye 2009
(17.1% on unit basis).
3
© 2010 Renesas Electronics America Inc.
All rights reserved.
Renesas Technology and Solution Portfolio
Microcontrollers
& Microprocessors
#1 Market share
worldwide *
Solutions
for
Innovation
ASIC, ASSP
& Memory
Advanced and
proven technologies
Analog and
Power Devices
#1 Market share
in low-voltage
MOSFET**
* MCU: 31% revenue
basis from Gartner
"Semiconductor
Applications Worldwide
Annual Market Share:
Database" 25
March 2010
** Power MOSFET: 17.1%
on unit basis from
Marketing Eye 2009
(17.1% on unit basis).
4
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All rights reserved.
Microcontroller and Microprocessor Line-up
Superscalar, MMU, Multimedia
High Performance CPU, Low Power
High Performance CPU, FPU, DSC
 Up to 1200 DMIPS, 45, 65 & 90nm process
 Video and audio processing on Linux
 Server, Industrial & Automotive
 Up to 500 DMIPS, 150 & 90nm process
 600uA/MHz, 1.5 uA standby
 Medical, Automotive & Industrial
 Up to 165 DMIPS, 90nm process
 500uA/MHz, 2.5 uA standby
 Ethernet, CAN, USB, Motor Control, TFT Display
 Legacy Cores
 Next-generation migration to RX
General Purpose
 Up to 10 DMIPS, 130nm process
 350 uA/MHz, 1uA standby
 Capacitive touch
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Ultra Low Power
Embedded Security
 Up to 25 DMIPS, 150nm process  Up to 25 DMIPS, 180, 90nm process
 190 uA/MHz, 0.3uA standby
 1mA/MHz, 100uA standby
 Application-specific integration  Crypto engine, Hardware security
Microcontroller and Microprocessor Line-up
Superscalar, MMU, Multimedia
High Performance CPU, Low Power
High Performance CPU, FPU, DSC
 Up to 1200 DMIPS, 45, 65 & 90nm process
 Video and audio processing on Linux
 Server, Industrial & Automotive
 Up to 500 DMIPS, 150 & 90nm process
 600uA/MHz, 1.5 uA standby
 Medical, Automotive & Industrial
 Up to 165 DMIPS, 90nm process
 500uA/MHz, 2.5 uA standby
 Ethernet, CAN, USB, Motor Control, TFT Display
 Legacy Cores
 Next-generation migration to RX
General Purpose
 Up to 10 DMIPS, 130nm process
 350 uA/MHz, 1uA standby
 Capacitive touch
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All rights reserved.
Ultra Low Power
Embedded Security
 Up to 25 DMIPS, 150nm process  Up to 25 DMIPS, 180, 90nm process
 190 uA/MHz, 0.3uA standby
 1mA/MHz, 100uA standby
 Application-specific integration  Crypto engine, Hardware security
Innovation
I-Cache
32KB
D-Cache
32KB
L2 Cache
256KB
MMU
UBC
INTC
DMAC
x6
H-UDI
CPG
500MHz
900 MIPS
FPU
MAC
LCDC
Others
WDT
TMU
x3
(ROM/SRAM)
VOU
VPU5F
H.264 D1@60fps
720p@30
2DG
32/16bit
SCIF
x6
CEU
x2
(Camera
I/F)
GPIO
10/100
Ethernet
MAC
w/DMA
CPU
I2C
x2
SDIO
x2
MEMORY
BEU x2
(Blend)
ANALOG
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MMC
NAND
KeyScan
JPEG
IrDA
SPU
ATAPI
24bit DSP
TIMER
Integration
7
DDR2
VEU x2
(Scaling)
USB-HS
Host or
Device
w/PHY
x2
BSC
Multi
media
I/O
Integration has made hardware easier but not
something that can be ignored
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Agenda
 Selecting clock circuit
 Power-On Reset (POR) and Low Voltage Detect (LVD)
 Watch Dog Timer (WDT) requirements
 Input Circuits
 Output Circuits
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How much time do you spend designing
hardware
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1.
Firmware Only
2.
Both Hardware and Firmware
3.
Hardware Engineer
4.
Architecture Level only
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Clock Circuit Selection
 Clocking circuit criteria




Startup time
Accuracy
Reliability
Cost
 Clock alternatives




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Crystal
Ceramic Resonator
On-Chip Oscillator
Compensated External Oscillator
(TXO)
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Clock Comparison – Arranged Best to Worst
Best
Cost
Reliability
External
(±25 ppm or
better)
On-Chip
On-Chip
On-Chip
(<10 cycles)
Crystal
(±50-200
ppm)
Resonator
($0.16)
w/caps
Resonator
Resonator
(100 uS)
Crystal
($0.20)
Crystal/
External
Crystal
(1-5 mSec)
Resonator
(>0.5% )
Worst
Startup
Time
Accuracy
On-Chip
(>2%)
External
($2.91)
External
(10 mSec)
0.5% = 5000 ppm
Rev. 1.00
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Clock Requirements – A few points
Standard
OCO Resonator
Special
Resonator
Crystal
TXO
CAN
Clock -3.6 hr
lost/month
Clock 30
min lost/yr
USBFS
USBHS
Uart
5%
1%
Ethernet
0.5% 0.1%
0.05% 0.01% 0.005%
5000ppm
500 ppm
Accuracy of Clock
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Power
RF
50 ppm
Power On Reset (POR)
 Do we need a POR circuit ?
 YES – you always need some POR
 POR Options
 Simple RC
 Internal POR
 External POR
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Simple RC Power On Reset
 Advantages
Vcc
 Inexpensive
 Simple
 Disadvantages
 Very dependent on Vcc rise time
 Not so simple
 Let’s look at an example
Design an RC circuit for M16C/62P
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MCU
Reset
RC Power On Reset Example
 Requirements (M16C/62P example)
 Reset <0.2 * Vcc for 2 mSec after min operating voltage
 Difficult if Vcc rises slowly
 Assume Vcc “snaps” to V operating
Vreset = Vcc (1-e-TC)
Min Op Voltage
Vcc
1 TC = 0.63 Vcc
0V
0.2 TC = 0.2 Vcc
0.2 Vcc
Reset 0V
> 2mSec
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This means RC design must
have 10 mSec TC
External Power On Reset
 Options
 Purchase a POR/Voltage Monitor Chip
 Design your own
 Purchased device
 Advantage
– Simple
– Reliable
 Disadvantage
– Cost
– Must match to the MCU
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External Power On Reset (Cont)VCC
 Design your own
R1
 Advantage
10K
– Cost ?
Res et
 Disadvantage
 Can be tricky to design
 Multiple components
R2
47K
2.7V
R3
100K
C1
2.2 uF
Zener set for MCU Vmin
Appendix has a full
calculation
R3 >> R2
Reset Line slope dV/dT is approximately
[(Vz-0.6)/R2)]/C1
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On-Chip Power On Reset
 Advantage
 Cost
 Already “tuned” to MCU
 Disadvantages
 MCU must have a POR
 May have rise time limitations on Vcc
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On-Chip Power On Reset - Example R8C/23
2.7 mA will charge 100 uF of capacitance to 2.7V in less than 100 mSec
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Low Voltage Detector (LVD) - (Brown-out
Detect)
 Do I need an LVD circuit?
 Probably
 Purpose of LVD
 Prevent operation of MCU with Voltage < Vcc
min
 Anticipate loss of voltage
– Save data
– Place system in “safe” state
 LVD only monitor MCU Vcc
 Consider all system power sources
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An example of using Voltage Detect
Slow Clock, Save Data to
EEPROM
Vcc
3.3-3.9
Vdet2
Vdet1
2.7-3.0
Power down mode entered
Restore Data, Run Full
Speed Clock
2.6
POR
Exit power down mode
Operating Range
3.0 – 5.5 20 MHz
2.7 – 3.0 10 MHz
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Ride Through
 Backup is not always Battery
 Example
 Ride through 30 seconds
 Do Not use Battery
Allow Voltage drop 3.1 to 2.8
Icc at 2 MHz = 1.5 mA
To
system
3.6V
SuperCap
0.1 uF
Vcc
R8C/27
I = C dV/dT
C = (I * dT)/dV
C = 0.15 Farad
* Above 0.22F @ 3.3V not common
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Watchdog Timer – Internal or External
 The internal WDT
 Recovers from software errors
 Don’t expect recovery from noise
 External WDT
 Sometimes required by safety standard
 Better chance recovering from noise
 Contained in many Voltage Monitors
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Input Circuits – Connecting Switches
 Physical connection, pull-up or pull-down
 Internal Pull-ups ?
V+
V+
Vcc
Vcc
R
MCU
Input
 Interrupt or no Interrupt
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Input
MCU
R
Pull–ups – How large can they be?
 Assume GPIO requires 0.8 Vcc for Vih
V+
 Use Vcc 3.0V for battery
 Pin leakage current 1.0 uA max
Vcc
R
MCU
Input
 Max resistance for pullup = 600 K (.6V/.1uA)
 Typically use between 10K and 68K
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Pull–ups when power is critical
V+
Vcc
Output
 S1 causes power loss when closed
 3V/600K = 5 uA
R
 Use port pin to drive pull-up
 Drive pin low once S1 active
 Poll status of S1 when active
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MCU
Input
S1
Level Translation
 Problem - Interfacing a 3V micro design to 5V LCD
 Writing to LCD
 R8C Voh is (Vcc – 0.5V) @ 5 mA
 No Problem
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Level Translation - Reading
 Unfortunately, R8C inputs are not 5V tolerant
+3.3V
+5V
R2
MCU
R1 = 30K
R2 = 20K
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R1
LCD
What about the other way
 It is a little different when MCU voltage is higher
 MCU requires 0.8 * Vcc (this is standard CMOS)
+5V
GPIO
+3V
R1
10K
R2
MCU
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4.7K
Sensor
Switch
A Power Output
 Designing a simple power drive
 Get Load requirement
 Divide by port output current
 This gives minimum hFE or Beta
 R2 = (Vout - 0.6)/(rated output current of port pin)
 D1 rated at load current
+12V
D1
+3V
Load
R2
680
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MCU
Unused Inputs
 Options
 Check HW manual
 Pull up or down
– Preferable to pull low
 Set to output
– Set output and low
– Vulnerable until set
– Draws power until set
32
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Questions?
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Summary
 Selecting clock circuit
 POR/LVD
 WDT requirements
 Input Circuits
 Output Circuits
34
© 2010 Renesas Electronics America Inc.
All rights reserved.
Innovation
I-Cache
32KB
D-Cache
32KB
L2 Cache
256KB
MMU
UBC
INTC
DMAC
x6
H-UDI
CPG
500MHz
900 MIPS
FPU
MAC
LCDC
Others
WDT
TMU
x3
(ROM/SRAM)
VOU
VPU5F
H.264 D1@60fps
720p@30
2DG
32/16bit
SCIF
x6
CEU
x2
(Camera
I/F)
GPIO
10/100
Ethernet
MAC
w/DMA
CPU
I2C
x2
SDIO
x2
MEMORY
BEU x2
(Blend)
ANALOG
© 2010 Renesas Electronics America Inc.
All rights reserved.
MMC
NAND
KeyScan
JPEG
IrDA
SPU
ATAPI
24bit DSP
TIMER
Integration
35
DDR2
VEU x2
(Scaling)
USB-HS
Host or
Device
w/PHY
x2
BSC
Multi
media
I/O
Appendix -
36
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To Interrupt or Not
 Probably Not
 Switches – except for low power wake-up
 A/D
 SPI
 Probably
 UART Receive/Transmit
 Timers
 Pulse counting or edge detection
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Polled Switch Routine
 Use Timer Tick for scheduling
 Setup below for 1 mSec tick
 Samples switch every 5 mSec
if ((tick_timer - last_sample_time)>4)){
if (SW1 )
SW1_count++;
else
SW1_count = 0;
if (SW1_count > 5){
SW1_state = ACTIVE;
.
.
.
last_switch_sample = tick_timer;
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© 2010 Renesas Electronics America Inc.
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External Power On Reset (Cont)
VCC
Assume Q beta = 75
Vcc = 5V, Vmin = 2.7V
R1
Set C1 to 0.22 uF
Charge time 10 mSec for 2.7V charge
I= C dv/dt = 0.22 uF * 0.5V/2mS = 50 uA
R1 sets zener current . Typical 0.5 ma
current would need 10K
 R2 = (2.7V – 0.6)/50 uA = 42K
 R3 just a discharge path 100K






R2
Res et
R3
C1
Zener set for MCU Vmin
R3 >> R2
Reset Line slope dV/dT is approximately
[(Vz-0.6)/R2)]/C1
39
© 2010 Renesas Electronics America Inc.
All rights reserved.
Renesas Electronics America Inc.