ID 115C: Low Pin Count V850: Small but Powerful MCU for portable
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Transcript ID 115C: Low Pin Count V850: Small but Powerful MCU for portable
ID 115C: Low Pin Count V850:
Small but Powerful MCU
for portable application
Renesas Electronics America Inc.
Bobby Wong
V850 Product Marketing Manager
12 October 2010
Version: 1.0
© 2010 Renesas Electronics America Inc. All rights reserved.
Mr. Bobby Wong
V850 Product Marketing Manager
Conduct competitive analysis and product
positioning
Responsible for product launch and next generation
product definition
Previous Experience
Over 10 years experience in embedded
system/ASIC design
Intel IA64 benchmarking and architecture research
Infineon TriCore and Tensilica Xtensa processor IP
application
Holds a BS EECS from UC Berkeley
Holds a MSEE degree from Stanford University
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© 2010 Renesas Electronics America Inc.
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Renesas Technology and Solution Portfolio
Microcontrollers
& Microprocessors
#1 Market share
worldwide *
ASIC, ASSP
& Memory
Advanced and
proven technologies
Solutions
for
Innovation
Analog and
Power Devices
#1 Market share
in low-voltage
MOSFET**
* MCU: 31% revenue
basis from Gartner
"Semiconductor
Applications Worldwide
Annual Market Share:
Database" 25
March 2010
** Power MOSFET: 17.1%
on unit basis from
Marketing Eye 2009
(17.1% on unit basis).
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© 2010 Renesas Electronics America Inc.
All rights reserved.
Renesas Technology and Solution Portfolio
Microcontrollers
& Microprocessors
#1 Market share
worldwide *
Solutions
for
Innovation
ASIC, ASSP
& Memory
Advanced and
proven technologies
Analog and
Power Devices
#1 Market share
in low-voltage
MOSFET**
* MCU: 31% revenue
basis from Gartner
"Semiconductor
Applications Worldwide
Annual Market Share:
Database" 25
March 2010
** Power MOSFET: 17.1%
on unit basis from
Marketing Eye 2009
(17.1% on unit basis).
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© 2010 Renesas Electronics America Inc.
All rights reserved.
Microcontroller and Microprocessor Line-up
Superscalar, MMU, Multimedia
High Performance CPU, Low Power
High Performance CPU, FPU, DSC
Up to 1200 DMIPS, 45, 65 & 90nm process
Video and audio processing on Linux
Server, Industrial & Automotive
Up to 500 DMIPS, 150 & 90nm process
600uA/MHz, 1.5 uA standby
Medical, Automotive & Industrial
Up to 165 DMIPS, 90nm process
500uA/MHz, 2.5 uA standby
Ethernet, CAN, USB, Motor Control, TFT Display
Legacy Cores
Next-generation migration to RX
General Purpose
Up to 10 DMIPS, 130nm process
350 uA/MHz, 1uA standby
Capacitive touch
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Ultra Low Power
Embedded Security
Up to 25 DMIPS, 150nm process Up to 25 DMIPS, 180, 90nm process
190 uA/MHz, 0.3uA standby
1mA/MHz, 100uA standby
Application-specific integration Crypto engine, Hardware security
Microcontroller and Microprocessor Line-up
Superscalar, MMU, Multimedia
High Performance CPU, Low Power
High Performance CPU, FPU, DSC V850
Up to 1200 DMIPS, 45, 65 & 90nm process
Video and audio processing on Linux
Server, Industrial & Automotive
Up to 500 DMIPS, 150 & 90nm process
600uA/MHz, 1.5 uA standby
Medical, Automotive & Industrial
Up to 165 DMIPS, 90nm process
500uA/MHz, 2.5 uA standby
Ethernet, CAN, USB, Motor Control, TFT Display
High Performance
Legacy Cores
Low Power
Next-generation migration to RX
VERY Small Packages
General Purpose
Instruction
Fetch
Data
Operand
Execute
Forward
DecodeUltra Low Power
Write
Back
Embedded Security
Up to 25 DMIPS, 150nm process Write
Branch/LD
Up to 10 DMIPS, 130nm process
Up to 25 DMIPS, 180, 90nm process
Memory
190 uA/MHz, 0.3uA standby
350 uA/MHz, 1uA standby
Back
1mA/MHz, 100uA standby
Pipe
Application-specific integration Crypto engine, Hardware security
Capacitive touch
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Innovation
Systems are smaller Designs are not less complicated
Oscilloscope
Battery-operated
Heat Scanner
DJ Mixer
Thermal Printer
Scanner
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Medical
equipment
V850 Low Pin Count Microcontrollers
Renesas offers a family of V850 32-bit
Microcontrollers that are High Performance,
Low Power and are available in Small
Packages.
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© 2010 Renesas Electronics America Inc.
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Agenda
Design Consideration of High Performance and Low Power
Portable Application
V850 energy efficient architecture
Many small packages to support design
Features Supporting Low Power Portable Application
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Key Takeaways
By the end of this session you will be able to:
Understand the Energy Efficient V850ES MCUs
Understand the different small packages
Understand the different operating modes and features of
V850ES for your portable application
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Portable Application Requirements
DJ Mixer
Oscilloscope
Heat Scanner
Thermal Printer
Medical
equipment
Scanner
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Leading Performance of V850ES MCU
V850 cores have leading performance in the industry
V850ES
MIPS32®24K®
1.5 DMIPS/MHz
AVR32 UC3
1.49 DMIPS/MHz
STM32 (Cortex M3)
1.25 DMIPS/MHz
ARM 9
1.04 DMIPS/MHz
ARM 7
0.95 DMIPS/MHz
ColdFire V2
0.94 DMIPS/MHz(SRAM)
ColdFire V2
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1.9 DMIPS/MHz
0.76 DMIPS/MHz (Flash)
1) Based on DMIPS v2.1
2) Numbers are based on publicly
available data sheets from the vendors
3) Data as of 2010/08/17
Low Power Design Problem
Cortex M3 Based MCU
Design Requirements
Performance – 40DMIPS (version 2.1)
Run at Maximum Performance for 1ms/second
STOP for the remainder of the second
Design Choices
DMIPS (2.1)
Stop
Current
Run
V850ES/Jx3-L
Time
2
DMIPS/MHz
CPU Freq.
1
Run Current
3.3V 25C1
A Cortex
40 DMIPS
1.25
36MHz
M3-based MCU
V850ES/Jx3-L
17.3mA
(Flash access needs 1 wait state)
39 DMIPS
1.95
20MHz
12mA
Stop Mode Current 1
uA
a Cortex-M3 based MCU
V850ES/Jx3-L
16
12
8
4
0
1
Stop Mode
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Based on values from specification stated in product datasheet
on internal benchmarking
2 Based
How Small are the Packages?
24.26mm
LQFP Packages
WQFN Packages
BGA Packages
(0.5mm Pitch)
(0.5mm Pitch)
(0.65/0.5mm Pitch)
80p
12mm
113p
8mm
64p
5mm
WQFN package
0.75mm Thinness
64p
10mm
48p
7mm
17.91mm
48p
7mm
40p
6mm
Only a small selection of packages
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V850 Bus Architecture
V850 MCU
CPU
Instruction
Fetch
Instruction Bus
On-chip Flash
External
Memory
DMA Control
External
Devices
Data Bus
Operand
Data Access
On-chip RAM
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Bus
Arbitration
External Bus
Control
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On-chip
Peripherals
Enhanced Pipeline Delivering High Performance
Regular
5-stage
pipeline
Enhanced 5-stage
pipeline
delivers
1.9 DMIPS/MHz
Instruction
Fetch
Instruction
Fetch
Operand
Decode
Execute
Branch/LD
Pipe
Early Address Calculation
Early address calculation reduces
branch penalty or load cycle
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Data
Memory
Forward
Write Back
Memory
Write Back
With Load/Store Buffer
Load/Store Buffer reduces 1 clock cycle
Enhanced Pipeline Delivering High Performance
Traditional 5-stage Pipeline: Branch R1, R2, Immediate
Instruction
Fetch
CLK1:
Branch instruction is fetched
Operand
Decode
CLK2:
Resolve
registers
Execute
Memory
Write Back
CLK3:
Compare and
Calculate Target address
Enhanced V850ES 5-stage Pipeline: BCOND, Immediate
Instruction
Fetch
CLK1:
Branch instruction is fetched
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Operand
Decode
Execute
Branch/LD
Pipe
CLK2:
Branch uses Condition Flag to decide
Calculate Target address
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Data
Forward
Write Back
Memory
Write Back
Reduce 1 cycle
Enhanced Pipeline Delivering High Performance
Traditional Pipeline: Load R1, R2, Immediate
Instruction
Fetch
CLK1:
LOAD instruction is fetched
Operand
Decode
CLK2:
Resolve
registers
Execute
Memory
CLK3:
Calculate Target address
Write Back
CLK4:
Load is executed
Enhanced V850ES Pipeline: SLOAD R1, Immediate
Instruction
Fetch
CLK1:
SLOAD instruction is fetched
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Operand
Decode
Execute
Branch/LD
Pipe
CLK2:
Add Immediate to a special register to
calculate Target address
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Data
Forward
Write Back
Memory
Write Back
CLK3:
Load is executed
Reduce 1 cycle
Enhanced Pipeline Delivering High Performance
Traditional Pipeline: Load could stall pipe
Instruction
Fetch
Operand
Decode
Execute
CLK1: LOAD
CLK2: Load
CLK3: Load
CLK2: Next Inst
CLK3: Next Inst
CLK4: Next inst.
Memory
Write Back
CLK4: Load is could stall the pipe
Enhanced V850ES Pipeline: Load/Store buffer reduces stall
LOAD
Next Inst
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Instruction
Fetch
Operand
Decode
Branch/LD
Pipe
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Execute
Data
Forward
Write Back
Memory
Write Back
Instruction Set For Performance and Fast Control
Fast computation
Saturated arithmetic operation
16x16 hardware multiplier to support fast multiplication
Single cycle shift with barrel shift hardware
Single cycle bit manipulation operation
Single cycle byte swap
Fast Response
Conditional Branch
– Branch based on Flag (C, Z and etc) hide 1 clock latency
Table of Function Call
– Faster address calculation for long call
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High Performance = Low Power?
Delivering High Performance and Low Power at the same
time sounds like a contradiction?
Higher Performance delivered by raising frequency will not
reduce power
Delivering more processing power by DMIPS/MHz can reduce
power consumption
Doing more work at a lower operating frequency means low
power and low EMI!!
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V850ES Energy Efficiency
Enhanced pipeline delivers high performance at 1.9DMIPS/MHz
(v2.1)
V850ES can operate at a lower frequency to achieve the same
processing performance as Cortex-M3 (1.25 DMIPS/MHz)1
Lower frequency consumes less power
DMIPS (2.1)
A Cortex
2
40 DMIPS
DMIPS/
MHz
CPU Freq.
1.25
36MHz
M3-based MCU
V850ES/Jx3-L
1
Run Current
Energy
3.3V 25C1
Efficiency
17.3mA
0.4mA/DMIPS
12mA
0.3mA/DMIPS
(Flash access needs 1 wait state)
39 DMIPS
1.95
1
20MHz
Source: http://www.arm.com/products/processors/cortex-m/cortex-m3.php
Based on values from specification stated in product datasheet
3 Based on internal benchmarking
2
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Circuit technique to reduce power in RUN
CPU
Flash
ROM
RAM
Memory
portion
Intelligent
power
management
I/O
Logic portion
Optimize Clock Tree Structure
Normal operation current (Typ.)
30mA
Maximize the choice of low
drive primitive cell
13mA
Jx3
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Jx3-L
Circuit technique to reduce power
ON/OFF management for Flash
CPU
Flash
ON
Always Powered ON
JG3-L
CPU
Flash
Flash
ON/OFF
OFF
Powered OFF during no fetch cycle
(e.g. DIV execution, 16bit instruction vs. 32bit fetch)
Activation management for RAM
JG3-L
CPU
RAM
Activate all RAM cell
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CPU
RAM
Activate only accessed RAM
Different Standby Modes and Options
Different operation modes to tailor application needs
Mode
Condition
32kHz
Main
PLL
Osc.
Ckt.
Osc.
Ckt.
RUN
ON2
ON
ON2
HALT
ON2
ON
IDLE1
ON2
IDLE2
STOP
CPU
Peripherals
Flash
RAM/Register
RTC
Others
ON
ON
ON
ON
ON
Retained
ON2
STOP
ON
ON
ON
ON
Retained
ON
ON2
STOP
STOP1
STOP1
ON
ON
Retained
ON2
ON
ON2
STOP
STOP1
STOP1
ON
OFF
Retained
ON2
STOP
STOP
STOP
STOP1
STOP1
Low Power
OFF
Retained
1
2
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Regulator
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RTC and some peripherals such as UART can be left on
32kHz oscillator/PLL can be switched on/off
Peripherals Support Low Power Design
V850ES/Jx3-L
UART/CSI opera table
When MCU is STOP
Tracks time
without waking up MCU
Track Vdd voltage
To manage system
Lots of Flash to store data
Eliminate EEPROM
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Real Time Calendar
Embedded registers for Second, Minute and etc
clk
16-bit
Sub Count
Second
Register
Minute
Register
Hour
Register
Day
Register
Week
Register
Calibration
Register
Eliminates waking up MCU every ½ second to track the time.
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Available in some products
Using Real Time Calendar To Save Current
Design Requirements
MCU wakes up every 15min
Do sensing and put time stamp on data
MCU w/
simple timer
current
MCU is woken up ½ second to
update time
MCU wakes up
for processing +
time stamping
MCU wakes up 1800 times
to update real-time in memory
time
15 min
time
15 min
MCU w/ RTC
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current
MCU is STOP during the 15min
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29
Real Time Calendar Hardware Calibration
Register
Hardware calibration to compensate crystal variance
Simplify factory calibration
Support field calibration
Adjustment from 61us to 11.3ms in 60 seconds
clk
16-bit
Sub Count
Second
Register
Minute
Register
Hour
Register
Day
Register
Week
Register
Calibration
Register
Calibration register add/subtract ticks to adjust variance
Available in some products
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Low Voltage Indicator Support Graceful Shutdown
Vbattery
Lithium Battery
Graceful Shutdown
Alert users to change battery
Save data in Flash
Alkaline Battery
Service Hours
Vdd
Low Voltage
Indicator
MCU
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Interrupt to
CPU
EEPROM Emulation Reduces Component Count
EEPROM /
Data Flash
MCU
High Density Flash
(Up to 1MB)
Data1
Data2
Data3
MCU
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Allocated Flash for
EEPROM Emulation
EEPROM Emulation Reduces Component Count
Same Data can be written to different physical Flash to
extend the number of updates
Physical
Flash
First call to
EEPROM_WRITE_DATA(data);
Valid Data
Allocated Flash for
EEPROM Emulation
Physical
Flash
Second call to
EEPROM_WRITE_DATA(data);
Old Data Valid Data
Inherently support “last valid” and “unroll”
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Allocated Flash for
EEPROM Emulation
Serial Interfaces That Can Wake Up MCU
Design Requirements
Wireless sensor network
Extend battery life as much as possible
Run to
maintain network
SPI
Radio +
Lower Layer MAC
STOP
MCU
Serial Interface can wake up MCU in STOP mode
External device supplies clock and data
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Serial Interfaces That Can Wake Up MCU
Design Requirements
Wireless sensor network
Extend battery life as much as possible
data
Run toup
Wake
maintain
network
MCU to process
SPI
Radio +
Lower Layer MAC
STOP
RUN
MCU
Serial Interface can wake up MCU in STOP mode
External device supplies clock and data
35
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V850ES MCUs Support Low Power Portable Applications
High performance
V850ES delivers 1.9DMIPS/MHz
Energy Efficient for Portable Application
V850ES/Jx3-L delivers 0.3mA/DMIPS
Small Packages
64-pin WQFN as small as 7x7mm. BGA in 5x5mm
Features support Low Power Portable Application
Real Time Counter, Low Voltage Indicator, EEPROM Emulation and more
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Commitment to Portable Application
Next generation V850ES/Jx4
1.5-2x performance improvement
Smaller packages to 33-pin
Today
V850ES
Jx3 series
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>50% reduction in current consumption
Specialized peripherals to reduce power
Innovation Possible
DJ Mixer
Oscilloscope
Heat Scanner
Thermal Printer
Medical
equipment
Scanner
38
© 2010 Renesas Electronics America Inc.
All rights reserved.
Thank You!
39
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Appendix
40
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MCU Naming Convention
Ｖ８５０ＥＳ ／ＪＧ ３ －Ｌ
CPU Core Type
V850
V850E
V850ES
V850E2
: V850
: V850E1
: V850ES
: V850E2
Line up
H
J
M
I
: 5V GP
: 3V GP
: High end GP
: Motor ASSP
Spec/ Pin count
C : 40/48pin
E : 64pin
F : 80pin
G : 100pin
H : 128pin
J : 144pin
K : 176pin
L : 208pin
“x” means a wildcard
V850ES/Jx3-L, V850ES/Hx3
Generation
The bigger the number, the
later the generation
Option
-L : Low Power
-H : High Performance/USB
-U/-E : USB Host/Ethernet
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V850 MCU Products in 2010
General Purpose
Ultra Low Power
General Purpose
V850ES/Jx3
V850ES/Jx3-L
62 DMIPS v2.1
STOP Current 1.5uA
81 DMIPS v2.1
USB Device
Max Freq: 32MHz
Voltage: 2.85 – 3.6V
Pins: 100-144
Flash: 385-1024 KB
RAM: 32-60 KB
Max Freq: 20MHz
Voltage: 2.85-3.6V
Pins: 80 - 100
Flash: 256 - 512KB
RAM: 32 - 40KB
Max Freq: 48MHz
Voltage: 2.85-3.6V
Pins: 48 -128
Flash: 16-512 KB
RAM: 8-56KB
Connectivity
V850ES/Jx3-H
V850ES/Jx3-U
Low Power
Connectivity
V850ES/Jx3-L
USB Device
Max Freq: 20MHz
Voltage 2.85-3.6V
Pins: 100
Flash: 256 - 512 KB
RAM: 40 KB
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81 DMIPS v2.1
USB Device + Host
Max Freq: 48MHz
Voltage 2.85-3.6V
Pins: 100-128
Flash: 384-512 KB
RAM: 48-56KB
V850ES/Jx3-E
84 DMIPS v2.1
Eth MAC + USB Device
Max Freq: 50MHz
Voltage: 2.85-3.6V
Pins: 128-144
Flash: 256-512 KB
RAM: 76-128KB
Scalable Family to Meet Different Cost Structure
Jx3
1 MB
Jx3-L
768 KB
512 KB
Jx3
Jx3
Performance: 39 – 90 DMIPS (v2.1)
Packages: 40 – 144 Pins
Flash Memory: 16k - 1M bytes
Jx3
Jx3-U
Jx3-E
Jx3-U
Jx3-H
Jx3-H
Jx3
Jx3-L
Jx3-E
Jx3
Jx3-L
Jx3-E
384 KB
2010/2011 Product Expansion
Jx3-U
Jx3-U
Jx3-H
Jx3-H
Jx3
Jx3-L
Jx3
Jx3-L
Jx3-E
256 KB
128 KB
Jx3-H
Jx3-H
Jx3-H
Jx3-H
Jx3-L
Jx3-L
Jx3-L
Jx3-H
Jx3-H
Jx3-H
Jx3-L
Jx3-L
Jx3-L
Jx3-L
Jx3-L
Jx3-L
Jx3-H
Jx3-L
Jx3-L
Jx3 General Purpose
64 KB
32 KB
16 KB
43
Jx3-H
Jx3-H
Jx3-H
Jx3-L Low Power
Jx3-L
Jx3-L
Jx3-L
Jx3-L Low Power + USB device
Jx3-H
Jx3-H
Jx3-H
Jx3-L
Jx3-L
Jx3-L
Jx3-E Ethernet + USB device
Jx3-H
Jx3-H
Jx3-H
Jx3-U USB host + USB device
Jx3-L
Jx3-L
Jx3-L
Jx3-H USB device
40pin
48pin
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64pin
80pin
100pin
128pin
144pin
Renesas Electronics America Inc.