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EMC Models
Models – What for ?
IC designers want to predict EMC before fabrication
Noise margin
Switching Noise on Vdd
 IC designers want to predict power integrity and EMI during design cycle
to avoid redesign
 EMC models and prediction tools have to be integrated to their design
flows
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March 2008
Models – What for ?
Equipment designers want to predict EMC before fabrication
© Siemens Automotive Toulouse
 Most of the time, EMC measurements are performed once the equipment
is built.
 No improvements can be done at conception phase.
 Predict EMC performances  IC, board, equipment optimizations
 However, need of non-confidential IC models (black box models)
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EMC of IC models
EMC Models depends on the targeted complexity, the level of
confidentiality of information.
Level
Equipment
Board
V, Z
100 V(f), 100 Z(f)
101 dipoles
Dipoles
Component
ICEM
101 R,L,C,I
LEECS
Physical
102 R,L,C,I
Expo
low
medium
104 R,L,C,I
PowerSI
high
spice
x-high
106 R,L,C,I
Complexity
Confidentiality
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EMC of IC model
The model of an IC can be derived from its physical architecture.
It includes the core and package model.
Model of the die :
•
•
•
•
Core
IC
Core
internal activity (core)
on-chip decoupling
supply network
I/O structure
Model of the package :
• R,L,C
• Transmission line
Package
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EMC of IC models
General flow to build an EMC model and predict EMC performances
Test bench Model
Test board Model
Package Model
Core – I/O
Model
EMC Model for
the circuit
Simulated Emission
spectrum
Electrical
Simulation
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Core model
Model core activity: noise source
Physical Transistor
level (Spice)
Interpolated
Transistor level
Gate level Activity
(Verilog)
Activity estimation
from data sheet
Huge simulation
Limited to analog blocks
Difficult adaptation to
usual tools
Limited to 1 M devices
Simple, not limited
Fast & accurate
Very simple, not limited
Immediate, not accurate
Activity1200
1000
800
600
400
200
00
Extraction
20
40
60
80
100
7
120
140
time (ns)
March 2008
Equivalent
Current
generator
Core model
Model The IC using a complete power supply distribution network
Chip model
Package model
Package model
Floorplanning,
physical layout
Vdd2
Chip
model
Vss2
Vdd1
Elementary cell
Vss1
 Full chip switching noise analysis, mapping of voltage drop, evaluation of
power integrity, crosstalk, EMI, effect of on-chip decoupling.
 Very accurate but large netlists.
 Too much complex to add PCB model.
 Adapted for IC designer issues.
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Core model
Model core activity: Tool example - PowerSI
Layout
Silicium voltage drop map
PowerSI - Real-time voltage noise simulation (right), including on-chip decoupling
capacitors, shows a more stable on-chip power supply © Sigrity http://www.sigrity.com
Accurate but high level of complexity
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Core model
Model The IC using double LC system
Example of measurement of IC conducted emission
Emission
Level (dBµV)
1st resonance
Envelop of spectrum
2nd resonance
Frequency
(MHz)
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Core model
Model The IC using double LC system
IC model
Package model
ICEM model
(IEC 62014-3)
External
VDD
External
VSS
Rvdd
Lvdd
LPackVdd
Cd
LPackVss
Cb
Rvss
Primary
resonance
Ib
Lvss
Secondary
resonance
Emission
level
Low L,C values =>
High resonant frequency
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Frequency
March 2008
IO Model
IBIS: Input Buffer I/O specification
[Component] Fx45H725
IBIS
[Manufacturer] Finex
[Package]
| variable typ min max
|
R_pkg 800m 500m 950m
L_pkg 6nH 5.5nH 7.5nH
C_pkg 8pF 4pF 10.5pF
[Pin] signal model R_pin L_pin C_pin
1 /1OE in1 921m 7.25nH 10.1pF
2 1Y1 out 1 916m 7.17nH 9.94pF
…
file
Input driver I(V)
characteristics
Output driver I(V)
characteristics
Very important for :
 I/O switching noise prediction
 I/O immunity prediction
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EMC Guidelines
Summary
1. Golden Rules for low emission
• Power supply routing strategy
• Decoupling capacitance
• Reduction of core noise
• Reduction of IO noise
2. Golden Rules for low susceptibility
• Decoupling capacitance
• Isolation of Noisy blocks
• Reduce desynchronization issues
• Improve noise immunity of IOs
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Golden Rules for Low Emission
Rule 1: Power supply routing strategy
A) Use shortest interconnection to reduce the serial inductance
•
•
•
Inductance is a major source of resonance
Each conductor acts as an inductance
Ground plane modifies inductance value (worst case is far from ground)
Reducing inductance
decreases SSN !!
Lead: L=0.6nH/mm
Bonding: L=1nH/mm
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March 2008
Golden Rules for Low Emission
Rule 1: Power supply routing strategy
A) Use shortest interconnection to reduce the serial inductance
Leadframe package:
L up to 10nH
Die of the IC
Long
leads
bonding
Far from ground
PCB
Short
leads
Flip chip package:
L up to 3nH
Die of the IC
balls
Close from ground
Requirements for high speed microprocessors : L < 50 pH !
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Golden Rules for Low Emission
Rule 1: Power supply routing strategy
B) Place enough supply pairs: Use One pair (VDD/VSS) for 10 IOs
9 I/O ports
Fail
Correct
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Golden Rules for Low Emission
Rule 1: Power supply routing strategy
C) Place supply pairs close to noisy blocks
Current density simulation
Layout view
Memory
PLL
Digital core
VDD / VSS
VDD / VSS
VDD / VSS
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Golden Rules for Low Emission
Rule 1: Power supply routing strategy
D) Place VSS and VDD pins as close as possible
• to increase decoupling capacitance that reduces fluctuations
• to reduce current loops that provoke magnetic field
Added
contributions
Lead
Current
loop
Reduced
contributions
EM wave
EM wave
current
EM field
current
Die
Lead
currents
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March 2008
Golden Rules for Low Emission
Rule 1: Power supply routing strategy
Case study 2:
Case 1 : Infineon Tricore
Case 2 : virtex II
Worst case
not enough supply pairs,
bad distribution & dissymmetry
Not ideal
Not enough supply for IOs :
(core emission is lower than IO one)
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March 2008
Golden Rules for Low Emission
Rule 1: Power supply routing strategy
Case study 2:
2 FPGA , same power supply, same IO drive, same characteristics
Supply strategy very different !
• More Supply pairs for IOs
• Better distribution
courtesy of Dr. Howard Johnson, "BGA Crosstalk", www.sigcon.com
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March 2008
Golden Rules for Low Emission
Rule 1: Power supply routing strategy
Case 1: low emission due to
a large number of supply
pairs well distributed
Case 2: higher emission
level (5 times higher)
courtesy of Dr. Howard Johnson, "BGA Crosstalk", www.sigcon.com
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Golden Rules for Low Emission
Rule 2: Add decoupling capacitance
 to keep the current flow internal
 Local energy tank
Parasitic emission
 to reduce the supply voltage
(dBµV)
swing
Volt
No
decoupling
time
time
Internal voltage drop
80
70
60
10-100 nF 50
decoupling 40
30
20
10
0
-10
1
Customer’s
specification
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10 – 15 dB
Efficient on
one decade
10
100
Frequency (MHz)
March 2008
1000
Golden Rules for Low Emission
Rule 2: Add decoupling capacitance
Power distribution network
Power
Electrolytic
supply
bulk capacitor
Voltage
regulator
Ground
PCB planes
Ferrite bead
1 µF – 10 mF
DC – 1 KHz
HF ceramic
capacitor
1 KHz – 1 MHz
On chip
interconnections
Vdd
100 nF – 1 nF Vss
1 MHz – 100 MHz
< 100 MHz
Power distribution network design :
Z Vdd - Vss
Target impedance Zt (0.25 mΩ)
Freq range
Vdd  ripple max
Zt 
current
Frequency
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Golden Rules for Low Emission
Rule 2: Add decoupling capacitance
On chip decoupling capacitance versus technology and complexity:
Intrinsic on-chip supply
capacitance
65nm
100nF
90nm
0.18µm
10nF
0.35µm
1.0nF
100pF
Devices on
chip
10pF
100K
1M
10M
100M
1G
Example: in 65nm technology, for a 200 Million devices on chip the intrinsic capacitance is 10nF
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Golden Rules for Low Emission
Rule 3: Reduce core noise
•
•
•
Reduce operating supply voltage
Reduce operating frequency
Reduce peak current by optimizing IC activity, using distributed
clock buffers, turning off unused circuitry, avoiding large loads,
creating several operation mode
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Golden Rules for Low Emission
Rule 3: Reduce core noise
•Add a controlled jitter on clock signal to spread the noise spectrum
Clock out
Clock in
T
T+/-Δt
Pseudorandom
noise
Spread spectrum
frequency modulation
P
specification
+/-Δf
f
+/-Δf
f
1/T
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March 2008
Golden Rules for Low Emission
Rule 3: Reduce core noise
• Asynchronous design spreads noise on all spectrum (10 dBµV reduction)
data
request
acknowledgment
data
clock
Synchronous block
Asynchronous block
specification
f
1/T
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Golden Rules for Low Emission
Rule 4: Reduce I/O noise
•Minimize the number of simultaneous switching lines (bus coding)
•Reduce di/dt of I/O by controlling slew rate and drive
Tr1
Tr2
SR
Emission
level
1/Tr2
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1/Tr1
f
March 2008
Golden Rules for Low susceptibility
Rule 1: Decoupling capacitance is also good for immunity
Immunity level
(dBm)
Decoupling
capacitance
• DPI aggression of a digital core
• Reuse of low emission design rules
for susceptibility
• Efficiency of on-chip decoupling
Substrate
isolation
combined with resistive supply path
No rules to reduce
susceptibility
Work done at Eseo France
(Ali ALAELDINE)
Frequency
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March 2008
Golden Rules for Low susceptibility
Rule 2: Isolate Noisy blocks
Bulk isolation
Why ?
• To reduce the propagation of
switching noise inside the chip
• To reduce the disturbance of
sensitive blocks by noisy blocks
(auto-susceptibility)
How ?
• by separate voltage supply
• by substrate isolation
• by increasing separation between
sensitive blocks
• By reducing crosstalk and
parasitic coupling at package level
Noisy blocks
Standard
cells
Far from
noisy blocks
Analog
Separate supply
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March 2008
Golden Rules for Low susceptibility
Rule 3: Reduce desynchronization issues
• Synchronous design are sensitive to
propagation delay variations due to
jitter (dynamic errors)
• Improve delay margin to reduce
desynchronization failures in
synchronous design
15 dB
• Asynchronous logic design is less
sensitive to delay compared to
synchronous design
Work done at INSA Toulouse/TIMA Grenoble
(Fraiddy BOUESSE)
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March 2008
Golden Rules for Low susceptibility
Rule 4: Improve noise immunity of IOs
• Add Schmitt trigger on digital input buffer
• Use differential structures for analog and digital IO to reject common mode
noise
2 dB
Schmitt trigger
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March 2008
Conclusion / Future
of EMC
Future of EMC
Scaling leads to an increase of transient currents
=> EMI and SSN problems get worse
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Current Peak
(A/mm²)
50
40
30
20
10
0
0.5 µm
0.35 µm 0.25 µm 0.18 µm 0.13 µm
90 nm
65 nm
45 nm
32 nm
Technology
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March 2008
Future of EMC
Towards complex systems, system on chip, system on package
=> Increase of emission level in a new frequency band (critical)
Critical frequency bands
Emission dBµV
100
80
New frequency
band
(1-10GHz)
System
on chip
60
40
20
0
10MHz
100MHz
1GHz
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10GHz
March 2008
Frequency
Future of EMC
Less noise margin :
=> 100mV in 2015 !!!!
Supply voltage
10V
External voltage
90nm
0.25m
1V
45nm
0.18m 0.13m
32nm
22 nm
18 nm
65nm
Internal voltage
Noise margin or
static margin
0.1V
Year
1995
2000
2005
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2010
2015
March 2008
Future of EMC
Most of EMC measurement methods are limited to 1 GHz.
IEC 61967-2
(TEM : 1GHz)
IEC 61967-3/6
(Near field scan, 5GHz)
IEC 61967-4
(1/150 ohm, 1 GHz)
IEC 62132-2
(BCI, 1 GHz)
IEC 61967-5
(WBFC, 1 GHz)
IEC 61967-7
(Mode Stirred Chamber:
18 GHz)
IEC 61967-2
(GTEM 18 GHz)
IEC 62132-3
(DPI, 1 GHz)
How characterizing accurately emission and
susceptibility of ICs up to 10 GHz?
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March 2008
Future of EMC
Models become more and more complex
 Circuits more complex (System-on-chip, System-in-package)
 Power distribution networks become larger, more and more IOs
 More and more parasitic coupling paths (substrate coupling,
package coupling)
 Modeling at high frequency ? How ensure accuracy and efficiency ?
Radiation
Chip stacking
System-InPackage
resonance
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Passive
devices
Crosstalk
via
Substrate
March 2008
Flip-chip
Vdd
Vss
Future of EMC
Developing new design guidelines
 Customers requirements are more and more constraining
 Off-chip decoupling capacitor are limited to several hundred MHz
 New technologies require less and less power distribution network
impedance
 Need of efficient techniques to reduce emission and improve immunity
to RFI
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March 2008
Conclusion

With technology scale down, ICs become more sensitive and
emissive.

EMC of ICs has become a major concerns for ICs suppliers

Standardization groups are working on EMC characterization
method (need to address high frequency)

Needs for simulation models and tools to predict ICs EMC
performances before fabrication

New EMC oriented design rules and techniques have to be
developed to ensure future ICs EMC compliance
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March 2008
Références
Books
www.springeronline.com
Tools
Workshops
www.ic-emc.org
www.emccompo.org
Standards www.iec.ch
• IEC 61967, 2001, Integrated Circuits emissions
• IEC 62132, 2003, integrated circuits immunity
• IEC 62014-3, 2003, Integrated Circuit Model
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