Transcript Rule 1: Power supply routing strategy

EMC of IC models
 The model of an IC can be derived from its physical architecture.
 It includes the core and package model.
Model of the die :
Core
IC
Core
•
•
•
•
internal activity (core)
on-chip decoupling
supply network
I/O structure
Model of the package :
• R,L,C
• Transmission line
Package
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IC model
Model core activity : extract noise source
32 bit
processor
500 MHz
16 bit
processor
16 MHz
Extraction of internal current waveform
I
I
3A
100 mA
time
time
62.5 ns
2 ns
1st order assumption : model core activity by triangular waveform current source
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IC model
Model core activity: noise source
Physical Transistor
level (Spice)
Interpolated
Transistor level
Gate level Activity
(Verilog)
Activity estimation
from data sheet
Huge simulation
Limited to analog blocks
Difficult adaptation to
usual tools
Limited to 1 M devices
Simple, not limited
Fast & accurate
Very simple, not limited
Immediate, not accurate
Activity1200
1000
800
600
400
200
00
Extraction
20
40
60
80
100
120
140
Equivalent
Current
generator
time (ns)
3
IC model
Model core activity: Tool example - PowerSI
Layout
Silicium voltage drop map
PowerSI - Real-time voltage noise simulation (right), including on-chip decoupling
capacitors, shows a more stable on-chip power supply © Sigrity http://www.sigrity.com
Accurate but high level of complexity
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Package model
Input Buffer I/O specification
(IBIS) – R,L,C for each pin
[Component] Fx45H725
[Manufacturer] Finex
[Package]
| variable typ min max
|
R_pkg 800m 500m 950m
L_pkg 6nH 5.5nH 7.5nH
C_pkg 8pF 4pF 10.5pF
[Pin] signal model R_pin L_pin C_pin
1 /1OE in1 921m 7.25nH 10.1pF
2 1Y1 out 1 916m 7.17nH 9.94pF
…
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EMC model example
Conducted/Radiated emission prediction
Emission
spectrum
dBµV
measurement
simulation
ICEM model
MHz
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EMC model example
Near-field emission prediction
Package model
with 13 leads
Scan area
Simulation of H field at
Measurement of H field
32 MHz
at 32 MHz
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Design issues
EMC for Integrated Circuits requires various expertise
High frequency measurement
High frequency modelling
2D, 3D modelling
Electrical modelling
IC design
IC floorplan
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6. EMC guidelines
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Basic concepts to reduce emission and
susceptibility
Remember the influent parameters on emission and susceptibility
Emission:
Susceptibility:
Control IC internal activity
Minimize circuit output load
Control
effect
of
IC
interconnections (decoupling)
Control effect of PCB
interconnections (decoupling)
Control effect of PCB interconnections
(decoupling)
Control effect
(decoupling)
of
IC
interconnections
Control Impedance of IC nodes
Reduce non linear effects of active devices
Improve block own susceptibility
Techniques used to reduce emission and/or susceptibility
issues are based on these principles
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Golden Rules for Low Emission
Rule 1: Power supply routing strategy
A) Use shortest interconnection to reduce the serial inductance
•
•
•
Inductance is a major source of resonance
Each conductor acts as an inductance
Ground plane modifies inductance value (worst case is far from ground)
Reducing inductance
decreases voltage bounce !!
Lead: L=0.6nH/mm
Bonding: L=1nH/mm
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Golden Rules for Low Emission
Rule 1: Power supply routing strategy
A) Use shortest interconnection to reduce the serial inductance
Leadframe package:
L up to 10nH
Die of the IC
Long
leads
bonding
Far from ground
PCB
Short
leads
Flip chip package:
L up to 3nH
Die of the IC
balls
Close from ground
Requirements for high speed microprocessors : L < 50 pH !
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Golden Rules for Low Emission
Rule 1: Power supply routing strategy
B) Place enough supply pairs: Use One pair (VDD/VSS) for 10 IOs
9 I/O ports
Fail
Correct
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Golden Rules for Low Emission
Rule 1: Power supply routing strategy
C) Place supply pairs close to noisy blocks
Current density simulation
Layout view
Memory
PLL
Digital core
VDD / VSS
VDD / VSS
VDD / VSS
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Golden Rules for Low Emission
Rule 1: Power supply routing strategy
D) Place VSS and VDD pins as close as possible
• to increase decoupling capacitance that reduces fluctuations
• to reduce current loops that provoke magnetic field
Added
contributions
Lead
Current
loop
Reduced
contributions
EM wave
EM wave
current
EM field
current
Die
Lead
currents
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Golden Rules for Low Emission
Rule 1: Power supply routing strategy
Case study 1:
Case 1 : Infineon Tricore
Worst case
not enough supply pairs,
bad distribution & dissymmetry
Case 2 : virtex II
Not ideal
Not enough supply for IOs :
(core emission is lower than IO one)
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Golden Rules for Low Emission
Rule 1: Power supply routing strategy
Case study 2:
2 FPGA , same power supply, same IO drive, same characteristics
Supply strategy very different !
• More Supply pairs for IOs
• Better distribution
courtesy of Dr. Howard Johnson, "BGA Crosstalk", www.sigcon.com
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Golden Rules for Low Emission
Rule 1: Power supply routing strategy
Case study 2:
Case 1: low emission due to
a large number of supply
pairs well distributed
Case 2: higher emission
level (5 times higher)
courtesy of Dr. Howard Johnson, "BGA Crosstalk", www.sigcon.com
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Golden Rules for Low Emission
Rule 2: Add decoupling capacitor
 Keep the current flow internal
 Local energy tank
 Reduce power supply voltage
drops
Parasitic emission
(dBµV)
80
70
60
10-100 nF 50
time
decoupling 40
30
time
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Internal voltage drop
10
0
-10
The most popular and
1
Volt
Customer’s
specification
No
decoupling
efficient solution !!!
10 – 15 dB
Efficient on
one decade
10
100
Frequency (MHz)
1000
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Golden Rules for Low Emission
Rule 2: Add decoupling capacitor on power distribution network
Power
supply
Voltage
regulator
Ground
Electrolytic
bulk capacitor
PCB planes
Ferrite bead
1 µF – 10 mF
DC – 1 KHz
HF ceramic
capacitor
1 KHz – 1 MHz
On chip
interconnections
Vdd
100 nF – 1 nF Vss
1 MHz – 100 MHz
> 100 MHz
Power distribution network design :
Z Vdd - Vss
Target impedance Zt (0.25 mΩ)
Freq range
Frequency
Vdd  ripple max
Zt 
current
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Golden Rules for Low Emission
Rule 2: Add decoupling on-chip capacitor
Intrinsic on-chip supply
capacitance
100nF
90nm
65nm
0.18µm
10nF
0.35µm
1.0nF
100pF
 Very high efficient decoupling
above 100 MHz (where PCB
decoupling capacitors become
inefficient) …
 … But space consuming
 Fill white space with decap cells
 Use MOS capa. or MetalInsulator-Metal (MIM) capa.
Devices on chip
10pF
100K
1M
10M
100M
On chip decoupling capacitance versus
technology and complexity
1G
Capa cell for
local decoupling
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Golden Rules for Low Emission
Rule 3: Reduce core noise
 Reduce operating supply voltage
 Reduce operating frequency
 Reduce peak current by optimizing IC activity, using distributed
clock buffers, turning off unused circuitry, avoiding large loads,
creating several operation mode
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Golden Rules for Low Emission
Rule 3: Reduce core noise
•Add a controlled jitter on clock signal to spread the noise spectrum
Clock out
Clock in
T
T+/-Δt
Pseudorandom
noise
Spread spectrum
frequency modulation
P
specification
+/-Δf
f
+/-Δf
1/T
f
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Golden Rules for Low Emission
Rule 3: Reduce core noise
• Asynchronous design spreads noise on all spectrum (10 dBµV reduction)
data
request
acknowledgment
data
clock
Synchronous block
Asynchronous block
specification
1/T
f
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Golden Rules for Low Emission
Rule 4: Reduce I/O noise
•Minimize the number of simultaneous switching lines (bus coding)
•Reduce di/dt of I/O by controlling slew rate and drive
Tr1
Tr2
SR
Emission
level
1/Tr2
1/Tr1
f
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Golden Rules for Low Susceptibility
Rule 1: Add decoupling capacitance
Immunity level
(dBm)
• DPI aggression of a digital core
Decoupling
capacitance
• Reuse of low emission design rules
for susceptibility
• Efficiency of on-chip decoupling
combined with resistive supply path
Work done at Eseo France
(Ali ALAELDINE)
Substrate
isolation
No rules to reduce
susceptibility
Frequency
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Golden Rules for Low Susceptibility
Rule 2: Isolate Noisy blocks
Why ?
• To reduce the propagation of
switching noise inside the chip
• To reduce the disturbance of
sensitive blocks by noisy blocks
(auto-susceptibility)
How ?
• by separate voltage supply
• by substrate isolation
• by increasing separation between
sensitive blocks
• By reducing crosstalk and
parasitic coupling at package level
Bulk isolation
Noisy blocks
Standard
cells
Far from
noisy blocks
Analog
Separate supply
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Golden Rules for Low Susceptibility
Rule 3: Reduce desynchronisation issues
• Synchronous design are sensitive to
propagation delay variations due to
jitter (dynamic errors)
• Improve delay margin to reduce
desynchronization failures in
synchronous design
• Asynchronous logic design is less
sensitive to delay compared to
synchronous design
15 dB
Work done at INSA Toulouse/TIMA Grenoble
(Fraiddy BOUESSE)
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Golden Rules for Low Susceptibility
Rule 4: Improve noise immunity of IOs
• Add Schmitt trigger on digital input buffer
• Use differential structures for digital IO to reject common mode noise (as
Low Voltage Differential Signaling I/Os)
Schmitt trigger
2 dB
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Case study
StarChip #1
Your definitive solution for embedded electronics,16 bit MPU with 16 MHz
external quartz,
• on-chip PLL providing internal 133MHz operating clock.
• 128Kb RAM, 3 general purpose ports (A,B,C, 8bits)
Emission
Susceptible
• 4 analog inputs 12 bits, CAN interface
SIGNAL
Description
VDD
Positive supply
VSS
Logic Ground
VDD_OSC
Oscillator supply
VSS_OSC
Oscillator ground
PA[0..7]
Data port A (programmable drive)
PB[0..7]
Data port B (programmable drive)
PC[0..7]
Data port C (programmable drive) external 66MHz data/address
ADC In [0..3]
4 analog inputs (12 bit resolution)
CAN Tx
CAN interface (high power, 1MHz)
CAN Rx
CAN interface (high power, 1MHz)
XTL_1, XTL_2
Quartz oscillator 16MHz
CAPA
PLL external capacitance
RESET
Reset microcontroller
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Case study
StarChip #1
Initial floorplan
Reset
ADC [0..3]
VSS_Osc
CA
N
VDD_Osc
OSC
NC
NC
VDD
Capa
PortA
PortB
VSS
NC
NC
PortC
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StarChip #1
Your floorplan
Case study
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7. Conclusion / Future of EMC
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Future of EMC
Scaling leads to an increase of transient currents
400
Total Peak Current (A)
350
300
250
200
150
100
50
0
0.5 µm
0.35 µm
0.25 µm 0.18 µm
0.13 µm
90 nm
Technology
65 nm
45 nm
32 nm
25 nm
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Future of EMC
Towards complex systems, system on chip, system on package
Critical frequency bands
Emission dBµV
100
80
New frequency
band
(1-10GHz)
System
on chip
60
40
20
0
10MHz
100MHz
1GHz
10GHz
Frequency
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Future of EMC
Less noise margin
Supply voltage
10V
External voltage
90nm
0.25m
1V
45nm
0.18m 0.13m
32nm
22 nm
18 nm
65nm
Internal voltage
Noise margin or
static margin
0.1V
Year
1995
2000
2005
2010
2015
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Future of EMC
Susceptibility trends vs frequency
Immunity suddenly
decreases?
Immunity increases with
Freq
Barber, Herke, IEE Electromagnetic Hazard, 1994
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Future of EMC
Most of EMC measurement methods are limited to 1 GHz
IEC 61967-2
(TEM : 1GHz)
IEC 61967-3/6
(Near field scan, 5GHz)
IEC 61967-4
(1/150 ohm, 1 GHz)
IEC 62132-2
(BCI, 1 GHz)
IEC 61967-5
(WBFC, 1 GHz)
IEC 61967-7
(Mode Stirred Chamber:
18 GHz)
IEC 61967-2
(GTEM 18 GHz)
IEC 62132-3
(DPI, 1 GHz)
How characterizing accurately emission and
susceptibility of ICs up to 10 GHz?
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Future of EMC
Models become more and more complex
 Circuits more complex (System-on-chip, System-in-package)
 Power distribution networks become larger, more and more IOs
 More and more parasitic coupling paths (substrate coupling,
package coupling)
 Modeling at high frequency ? How ensure accuracy and efficiency ?
Radiation
Chip stacking
System-InPackage
resonance
Passive
devices
Crosstalk
via
Substrate
Flip-chip
Vdd
Vss
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Future of EMC
Developing new design guidelines
 Customers requirements are more and more constraining
 Off-chip decoupling capacitor are limited to several hundred MHz
 New technologies require less and less power distribution network impedance
 Need of efficient techniques to reduce emission and improve immunity
Electromagnetic bandgap
High density
MOS capacitance
Active noise
cancellation
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Conclusion
 With technology scale down, ICs become more sensitive and
emissive.
 EMC of ICs has become a major concerns for ICs suppliers
 Standardization groups are working on EMC characterization
method (need to address high frequency)
 Needs for simulation models and tools to predict ICs EMC
performances before fabrication
 New EMC oriented design rules and techniques have to be
developed to ensure future ICs EMC compliance
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