Transcript FFT

Graduate Institute of Electronics Engineering, NTU
102-1 Under-Graduate Project
Improving Timing, Area, and Power
Speaker: 黃乃珊
Adviser: Prof. An-Yeu Wu
Date: 2013/12/12
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Introduction
When design in RTL, the designer need to be
aware of timing, area and power issues.
Meeting timing is the most critical goal in
design. Only optimize for power or area after
timing is met.
Synthesis tools operate in gate level, and
cannot resolve all timing, area and power
issues.
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Timing Issues
 Timing v.s. Performance
 Latency
 How long does it take to complete a particular operation?
 Unit : ns, us, ms
 Throughput
 How many operations can be completed per second?
 Unit : Mbps, Gbps
Input
1bit output
Latency = 2 clock cycles
Throughput = 1bit/clock cycle
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Timing Requirement
To fit system throughput, the timing (clock
period) must be smaller than some value.
In IC design industry, the design must meet
timing with margin, and using worst-case
library model.
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How to Improve Timing?
While your clock cycle time does not fit system
specification
Pipelining : Exploits temporal parallelism
 Reduce the clock cycle time (clock period)
 Insert pipeline registers without changing coherence of the
data.
Parallel skill
 Decrease data flow of your design
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Pipelining
original
Tmax
fclock < 1/T max
data_in
Input
Registers
Output
Registers
Multi-level Logic
data_out
2-stage pipelining
data_in
data_out
Input
Registers
Comb
Logic
Pipeline
Register
Comb
Logic
Output
Registers
fpipeline < 2 / T max
Tmax/ 2
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Example 1 : Simple Circuit
original
3-stage pipelining
Critical path = 3 adders
Critical path = 1 adders
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Example 2 : Pipelined 16-bit Adder
clock
b[15:0]
a[15:0]
a[15:8]
b[15:8]
b[7:0]
a[7:0]
IR[16:9]
b
IR[32:25]
IR[24:17]
c_in
IR[8:1]
Input Register: IR[32:0]
IR[0]
a
c_out
c_in
sum
Pipeline Register: PR[7:0]
PR[24:17]
b
PR[16:9]
a
c_out
c_in
PR[8]
PR[15:0]
sum
sum[7:0]
c_out
Output Register: OR[16:0]
sum[15:0]
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Parallel Processing
original
Parallel processing
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Area Issues
Area = Cost.
During the design process, the designer should
be “area aware”.
Resource sharing
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Power Consumption in CMOS
Low power design is more and more
important in today’s chip design due to heat
dissipation, packaging, and portability needs.
Power Consumption
P   Nnode * CL *Vdd * fclock
2
Nnode : switching activity
fclock : clock frequency
CL : node capacitance
Vdd : power supply voltage
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Strategy for Low-Power Design (1/2)
Vdd is technology-dependent.
Pipelining
Parallel processing
 Execute tasks concurrently to improve throughput
 Increase the system’s overall sampling rate
 Incorporates multiple copies of hardware
CL can only be minimized by back-end design.
Optimize fclock and Nnode are the most practical
power reduction techniques.
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Strategy for Low-Power Design (2/2)
Reducing Clock Frequency
Design with clock rate that is ‘just right’
Clock Gating
Reducing switching activity
Avoid unnecessary circuit switching
Reducing switching activity at I/O pins
Use simple hardware if it gets the job done
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Example : Multiplier
original
Low-power design
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