Transcript Week 16 - Network and Systems Laboratory

Network and Systems Laboratory
nslab.ee.ntu.edu.tw
Network and Systems Laboratory
nslab.ee.ntu.edu.tw
Administration
 Week 17 (6/8): Term Project workshop
 No class, I will be here to help you work on your term
project
 Deadline for the lab exercises

Demo and turn on your codes before 2008/6/8 23:59
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Outline
 More peripherals
 Watchdog Timer
 Supply Voltage Supervisor (SVS)
 Direct Memory Access (DMA)
 Flash Memory Controller
 External 8Mbit Flash Memory: M25P80
 Temperature/humidity sensor: SHT11
 Low Power Modes
 MSP430 Software Coding Techniques
Network and Systems Laboratory
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Watchdog Timer
 Most embedded systems need to be self-reliant
 watchdog timer is a hardware
 that can watch for system hang
 reset the processor if any occur
 It is a counter
 counts down from some initial value to zero
 must select a counter value
 periodically restarts the counter

before it counts to zero
 If it counts to zero
 trigger a system reset
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Watchdog timer on MSP430
 16-bit timer, four software-selectable time intervals
 (clock source)/32768, (clock source)/8192, (clock
source)/512, (clock source)/64
 Can be configured into watchdog mode or interval
mode
 Watchdog mode: generate a reset when timer expired
 Interval mode: generate a interrupt when timer expired
 When power up, it is automatically configured in the
watchdog mode
 Initial ~32-ms reset interval using the DCOCLK.
 Must halt or setup the timer at the beginning
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Usage
ClockSource/32768:
 Stop watchdog timer
ClockSource/8192: WDTIS0
ClockSource/512: WDTIS1
 WDTCTL = WDTPW + WDTHOLD; ClockSource/64: WDTIS0 + WDTIS1
 Change watchdog timer interval
 WDTCTL = WDTPW+WDTCNTCL+(interval)
 Periodically clear an active watchdog
 WDTCTL |= WDTPW+WDTCNTCL
Password-protected: must include
the write password
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Example
Select clock source: ACLK
Select timer interval:
(clock source)/8192
= 32768Hz/8192
= 4Hz
Reset watchdog counter
Reset watchdog counter
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Supply Voltage Supervisor
 Monitor the AVCC supply voltage or an external
voltage
 Can be configured to set a flag or generate a reset
when the supply voltage or external voltage drops
below a user-selected threshold
 Comparison
 14 threshold levels for AVCC
 External input: SVSIN

compared to an internal level of approximately 1.2 V
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SVS Register
 SVSCTL
 VLDx
This bit will set to 1
if the voltage is
below threshold
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Example
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Direct Memory Access
 Transfers data from one address to another, without
CPU intervention
 Increase throughput and decrease power consumption
 DMA on MSP430
 Three independent transfer channels
 Configurable transfer trigger selections
 Timer, UART, SPI, ADC, …..
 Byte or word and mixed byte/word transfer capability
 Single, block, or burst-block transfer modes
 Block sizes up to 65535 bytes or words
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DMA Addressing Modes
Source/destination
address can be
configured to be
unchange/increment
/decrement after
each transfer
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DMA Transfer Modes
 Six transfer modes
 Single transfer, block transfer, burst-block transfer, repeated single
transfer, repeated block transfer, repeated burst-block transfer
 Single transfer
 Each transfer requires a separate trigger, DMA is disable after transfer

Must re-enable DMA before receive another trigger
 Repeated single transfer: DMA remains enable
 Another trigger start another transfer
 Block transfer
 Transfer of a complete block after one trigger, DMA is disable after
transfer
 Repeated block transfer: DMA remains enable,

Another trigger start another transfer
 Burst-block transfer
 Block transfers with CPU activity interleaved,
 Repeated burst-block transfer: DMA remains enable


Keep transferring
CPU executes at 20% capacity
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DMA Triggers
A transfer is triggered when
the CCIFG flag is set
A transfer is triggered when
USART0 receives new data
A transfer is triggered when
USART0 is ready to transmit
new data
A transfer is triggered by an
ADC12IFGx flag.
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Initialization And Usage
(DMACTL0)
Configure
transfer trigger
(DMA0SA)
Configure source
address
(DMACTL1)
Select transfer mode, addressing
mode, and/or other setting, and
enable DMA
(DMA0DA)
Configure destination
address
(DMA0SZ)
Configure block size
 Example
Repeated
single transfer
Use DMA to
transfer a string to
UART buffer, send
it out through UART
Source address is
incremented
source byte to
destination byte
DMA enable
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Others About DMA
 DMA Transfer Cycle Time
 DMA transfers are not interruptible by system
interrupts
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Flash Memory Controller
 MSP430 flash memory is bit-, byte-, and word-
addressable and programmable
 Segment erase and mass erase
 Minimum VCC voltage during a flash write or
erase operation is 2.7 V
 Program code are stored in the flash
 Unused flash memory can be use to store other data
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Flash Memory Characteristics
 Write in bit-, byte-, or word; erase in segment
 MSP430F1611 segment size
 Information memory: 128 bytes
 Main memory: 512 bytes
 Erase
 Make every bit in the segment as logic 1
 Write
 Generate logic 0 in the memory
 Flash endurance
 Maximum erase/write cycles
 In MSP430 datasheet


Minimum: 10000 cycles
Typical: 100000 cycles
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Flash Memory Operation
 Read, write, erase mode
 Default mode is read mode
 Write/erase modes are selected with the BLKWRT,
WRT, MERAS, and ERASE bits
 Flash Memory Timing Generator
 Sourced from ACLK, SMCLK, or MCLK
 Must be in the range from ~ 257 kHz to ~ 476 kHz

Incorrect frequency may result in unpredictable
write/erase operation
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Flash Memory Erase
Disable all
interrupts and
watchdog
(FCTL2)
Setup timing
generator
Re-enable
interrupt and
watchdog
(FCTL3)
lock flash
memory
(FCTL3)
Unlock flash
memory
Wait until erase
complete
(FCTL1)
Configure the
operation
Dummy write
 Example
Password protected
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Flash Memory Write
Disable all
interrupts and
watchdog
(FCTL2)
Setup timing
generator
Re-enable
interrupt and
watchdog
(FCTL3)
lock flash
memory
(FCTL3)
Unlock flash
memory
(FCTL1)
Configure the
operation
Wait until write
complete
Write to specific
memory address
 Example
Password protected
Network and Systems Laboratory
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Outline
 More peripherals
 Watchdog Timer
 Supply Voltage Supervisor (SVS)
 Direct Memory Access (DMA)
 Flash Memory Controller
 External 8Mbit Flash Memory: M25P80
 Temperature/humidity sensor: SHT11
 Low Power Modes
 MSP430 Software Coding Techniques
Network and Systems Laboratory
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M25P80




External Flash storage on Taroko
8 Mbit Flash Memory
SPI Bus Compatible Serial Interface
Memory organization
 16 sectors
 Each sector containing 256 pages
 Each page is 256 bytes
 Operations
 Erase: set all bit to 1
 Program(write): reset some bits to 0
 Read: read the content of the flash
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Signals And Connections
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SPI
 Master–Slave mode
 Synchronous protocol
 All transmissions are referenced to a common clock
 Clock generated by the master (MCU)
 Four main signals
 Master Out Slave In (MOSI): data from master to slave
 Master In Slave Out (MISO): data from slave to master
 Serial Clock (SCLK or SCK): clock
 Chip Select (CS): select particular peripheral when multiple
peripherals are connected to master
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Memory organization
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Instruction Set
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Operation
 Read Data Bytes (READ)
 Read data from memory
 Page Program
 Write bytes to a page
 Up to 256 bytes each time
 Sector Erase
 sets all bits to 1 inside
the chosen sector
 Bulk Erase
 Erase (sets to 1) all memory data
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Device Driver
 Download here
 http://nslab.ee.ntu.edu.tw/courses/wsn-labs-spring09/labs/m25p80Driver.rar
 Important functions in hal_m25p80.c
 void halM25p80Init(void)
 void m25p80PowerUp(void);
 void m25p80PowerDown(void);
 void m25p80PageWrite(UINT16 add, UINT8 *buff, UINT8
size);
 void m25p80PageRead(UINT16 add, UINT8 *buff, UINT8
size);
 void m25p80SectorErase(UINT8 add);
 void m25p80BulkErase(void);
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Functions
 void m25p80PageWrite(UINT16 add, UINT8 *buff, UINT8










size);
address range from 0x0000 to 0x0fff (4096 pages in total)
At most 256 bytes
Always write from the beginning of the page
void m25p80PageRead(UINT16 add, UINT8 *buff, UINT8 size);
address range from 0x0000 to 0x0fff (4096 pages in total)
At most 256 bytes
Always read from the beginning of the page
void m25p80SectorErase(UINT8 add);
address range from 0x00 to 0x0f (16 sectors in total)
Each sector is 65536 bytes
Network and Systems Laboratory
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Example
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Outline
 More peripherals
 Watchdog Timer
 Supply Voltage Supervisor (SVS)
 Direct Memory Access (DMA)
 Flash Memory Controller
 External 8Mbit Flash Memory: M25P80
 Temperature/humidity sensor: SHT11
 Low Power Modes
 MSP430 Software Coding Techniques
Network and Systems Laboratory
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SHT11
 Relative humidity and temperature sensors
 Digital output
 Manufacturer defined interface
 two wires bi-direction
1. Use a GPIO pin as clock (SCK), it
is always output direction
2. Use another GPIO as DATA,
dynamic setting it to input(read)
or output(write) direction
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Taroko Connections
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Start Transmission and Send Command
 How to start
 What are the commands available
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Pull-up
An Example: SHT11
 Timing diagram
Data pin in output
direction
Set data pin to input
direction, then SHT11
controls the DATA line
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Software Implementation
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Software Implementation
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Software Implementation
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Convert to Physical Values
 12-bit humidity, 14-bit temperature
 Temperature
 Humidity
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Device Driver
 Download here
 http://nslab.ee.ntu.edu.tw/courses/wsn-labs-spring09/labs/sht11Driver.rar
 Important functions in SHT1x_sensirion.c
 void sht1xInit();
 void sht1xReset();
 char sht1xMeasure(unsigned char *p_value,
unsigned char *p_checksum, unsigned char mode);
 void sht1xCalculate(float *p_humidity ,float
*p_temperature);
Network and Systems Laboratory
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Functions
 char sht1xMeasure(unsigned char *p_value, unsigned char







*p_checksum, unsigned char mode);
mode: { TEMP, HUMI }
Store measured value to *p_value
Store 8-CRC checksum to *p_checksum
void sht1xCalculate(float *p_humidity ,float
*p_temperature);
Convert measured value to physical value
Put the measured value in *p_humidity, *p_temperature
Result will also place in *p_humidity, *p_temperature
(overwrite)
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Example
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Outline
 More peripherals
 Watchdog Timer
 Supply Voltage Supervisor (SVS)
 Direct Memory Access (DMA)
 Flash Memory Controller
 External 8Mbit Flash Memory: M25P80
 Temperature/humidity sensor: SHT11
 Low Power Modes
 MSP430 Software Coding Techniques
Network and Systems Laboratory
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MSP430 Clock System
high-frequency
oscillator (optional)
digitally controlled oscillator
Clock Modules
DCOCLK
MSP430
Clock Signals
MCLK:
Master Clock
SMCLK:
Sub-main
clock
XT2CLK
LFXT1CLK
ACLK:
Auxiliary clock
32.768KHz fixed rate
Low-frequency/highfrequency oscillator
CPU
Peripherals:
Timer,
UART, …
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MSP430 Power Consumption
Characteristics
 Current increase with clock frequency
 Current increase with supply voltage
 Supply voltage vs frequency
 More active peripherals means more current
consumption
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Operating Modes
 MSP430 has six operating modes
 The operating modes take into account three
different needs
 Ultralow-power


Speed and data throughput
Minimization of individual peripheral current
consumption
 Turn off different clocks in different operating
mode
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Operating Modes
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Typical Current Consumption
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Low Power Modes
 Different low power mode disable different clocks
 Peripherals operating with any disabled clock are
disabled until the clock becomes active
 Wake up is possible through all enabled interrupts
 Returns to the previous operating mode if the status
register value is not altered during the ISR
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Code Flow
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Enter/Leave LPM
Intrinsic function
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Which LPM To Enter?
 Depends on your configuration
 MSP430 has a flexible clock system
 Clock signal can select different clock source
 Peripheral can be configure to use different clock
signal
 Which clock signal still require when system goes
to sleep
 Remember the peripherals that use the clock signal
will also be disabled
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Cautions
 Wakeup latency
 Clock module require some time to get stable


DCO: less than 6 μS
Low frequency oscillator (32.768KHz): hundreds of
milliseconds
 Temperature drift
 DCO change with temperature
 If temperature is possible to changes significantly,
re-calibrate DCO when leaving low power mode

If DCO varying too large, some peripherals might not
function correctly, ex. UART
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Typical Configuration
digitally controlled oscillator
Clock Modules
DCOCLK
XT2CLK
LFXT1CLK
MSP430
Clock Signals
MCLK:
Master Clock
SMCLK:
Sub-main
clock
ACLK:
Auxiliary clock
32.768KHz fixed rate
CPU
Peripherals:
Timer,
UART, …
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Useful Mode
 LPM0
 CPU, MCLK off
 DCO, SMCLK, ACLK on
 Power consumption: 60 μA (Taroko)
 SMCLK still required

Ex. UART use SMCLK
 LPM3
 CPU, MCLK, DCO, SMCLK off
 ACLK on
 Power consumption: 7 μA (Taroko)
 Only ACLK required

Timer use ACLK (time keeping)
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Principles for Low-Power Applications
 Maximize the time in LPM3
 Use interrupts to wake the processor and control
program flow
 Peripherals should be switched on only when
needed
 Use low-power integrated peripheral modules in
place of software driven functions
 For example: Timer PWM, DMA
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MSP430 Software Coding Techniques
 Using these methods can greatly reduce debug
time and/or provide additional robustness in the
field
 Some should be used in every program, while
some are situation dependent
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Techniques
 First Things First: Configure the Watchdog and
Oscillator
 Configuring the watchdog should be among the first
actions taken by any MSP430 program
 Using a low-frequency crystal on LFXT1 with a device
from the 4xx or 2xx families, the code should configure
the internal load capacitance (not for MSP430F1611)
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Techniques
 Always Use Standard Definitions From TI Header Files
 This is what we do
 Using Intrinsic Functions to Handle Low Power Modes
and Other Functions
Intrinsic
function
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Techniques
 Write Handlers for Oscillator Faults
 In MSP430F1611, you can only delay for some time to
ensure the low frequency oscillator to stable

The other MSP430 family has specific circuit to detect
 Increasing the MCLK Frequency
 Make sure you have enough voltage level to operate at
the frequency you set

Or unpredictable behavior
can occur
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Techniques
 Using a low-level initialization function
 Problem
 By default, when a C compiler generates assembly code, it
creates code that initializes all declared memory and inserts it
before the first instruction of the main() function
 In the event that the amount of declared memory is large
 The time required to initialize the long list of variables may be
so long that the watchdog expires before the first line of main()
can be executed
 Solution
 Disables the initialization of memory elements that don't need
pre-initialization
 __no_init int x_array[2500];
 Use a compiler-defined low-level initialization function
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Techniques
 In-System Programming (ISP)
 If using the MSP430 ISP functionality to write to flash
memory
1.
2.
3.
4.
Set the correct timing value (257 kHz to ~ 476 kHz)
Set the flash lock bit after the ISP operation is complete
Take care that the cumulative programming time
Provide sufficient VCC
 Using Checksums to Verify Flash Integrity
 Flash memory data may corrupt, use checksum to
verify flash integrity periodically