Transcript Lecture_9_ProcessVariation_36

Process Variation
Mohammad Sharifkhani
Reading
• Textbook, Chapter 6
• A paper in the reference
Introduction
• What is process variation?
– Deviation from intended or
designed values
• Types:
– Environmental
• Arise during circuit operation
– Power supply, temprature, etc.
– Physical
• Parametric variation of the
process
– Processing, masking, etc.
Introduction
• The variation do not
scale as much!
– Check ITRS
• Parameters under
variation for
interconnects:
– W, T, H, p (resistivity)
• Why is it important?
Introduction
• Why is it important?
– Interpath correlation  Yield
The max delay of
K path in a lot of chips
Introduction
• Intergate correlation
–  Yield
Introduction
• Impact on performance
Introduction
• Impact on Price!
Sources of Variation (Lithography)
• Lithography
– Sub-wavelength lithography
Sources of Variation: Lithography
• Optical Proximity
Correction (OPC)
– modifies layout to
compensate for
process distortions
– Add non-electrical
structures to layout to
control diffraction of
light Rule-based or
odelbased
Sources of Variation: Lithography
Gate Length Variation
Horizontal variation
Chemical Mechanical
Planarization(CMP)
Etch/polishing variation CMP)
• Vertically affects the wire caps, resistance,
etc.
Erosion and Dishing
Stress Induced Variability
Random Doping Variation
–RDF: Random location and distribution of the dopant atoms
 Vth variation of 10/sqrt(W) mV/um½
Environmental Sources:
Temperature
Environmental Sources: IR Drop
Categorization
Categorization
• Intra-die
– Within die variations
– Due to
• Layout patterns (e.g, two interconnects)
– Systematic, lithography, lens, etc.
• Wafer level trends (e.g, slanted plane)
– Induces mismatch (between different paths)
• Inter-die
–
–
–
–
Variation between nominally identical dies (on the same wafer)
Shift in the mean of a parameter (Vth, wire width)
Simplified distributions are possible to capture variance
Easier to model based on systematic trends on the wafer (bowl
shape  Speed)
Inter die vs. Intra die
Temporal variations
Temporal variation (short scale)
Lumped statistics
• Regardless of the
reason behind
variation
– Combination of reasons
• Find the mean,
variance for
individual
parameters
• Assuming
uncorrelated
• Results in worst
case scenarios
Survey of process variation
• Device geometry variation
– Film thickness variation
• Gate oxide; critical, yet well controlled. Causes
Inter-die variation
– Lateral dimension variation
• Lithography limitation, lens, etching, etc.; affects
effective length and width, both inter and intra die
variation
• Channel length variation dominates output current
characteristics, vth, etc.
Survey of process variation
• Device material parameter variation
– Doping variation; affects junction depth,
threshold voltage
• Drain eng. (Halo) gives rise to variation
• Intra-die variation
– Deposition variation; affects the resistivity
(silicide and metal)
• Variation in Contact and Line differences
Survey of process variation
• Effect on device electrical parameter
variation
– Vth variation; geometric variations, charge
trapped in oxide and RDF; 10% of the Vth of
the smallest device
– Leakage current exponential relationship
with Vth
Vth variation
Leakage vs. Freq.
Survey of process variation
• Effect on interconnect electrical parameter
variation
– Line width and line space variation; the smaller the
worse  resistance variation and capacitance
variation  coupling variation
– Metal thickness; resistance variation (up to 20% of
line thickness can be etched)
– Dielectric thickness; coupling capacitance variation;
deposition can vary up to 5%, polishing
– Contact and via size; resistance variation due to
etching, layer thickness
Modeling variation
• Statistical modeling
– Model parameter extraction;
• We can not measure L or W, but Ids for a given
Vgs. Model fitting using a number of devices.
• It is difficult and very inaccurate
• The process itself changes in time
• Worst case analysis and design is prefered
Worst-case analysis
• If we assume
all varying
parameters are
uncorrolated,
we end up with
an overly
pessimistic
situation
Worst case analysis
• Finding worst case situation that actually
happens
– Worst case models (corners)
– Provided by manufacturing companies
– If a design passes the design spec, it provides
an acceptable Yield
Spatial variation modeling
(mismatch)
• Have long been studied in Analog circuits
– The variance in the mismatch is twice as
much as the variance of individual variables
(if they are uncorrelated)
– If they are close  correlation
• Layout information needed ahead of time
– If averaging happens  less variance (e.g.,
larger devices mismatch  area)
Example
• An example will be shown in Timing
section