Multiple Gate

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Transcript Multiple Gate

Final
Presentation
Tri-Gate와 Spacer의
상관관계에 대한 특성연구
Week 15th
200801190 정성인
200901037 백근우*
201101174 김기연
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01) Intro
02) Body
03) Remarks
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01. Introduction
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Mu l ti pl e
G a t eMultiple Gate
Specification
Limitation
Equipment
1. Trend in Semiconductor
- Super-high Speed
- Super-large Integration
- Low-power Technology
2. Problems with SCE(Short Channel Effect)
-
Reduction of sub-threshold voltage
Reduction of mobility
Increase of leakage current
Increase of resistance between source and drain
3. Ideal Model
- Multiple Gate(MuGFET)
- It has great performance on gate control
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Mu l ti pl e
G a t eMultiple Gate
Specification
2011. 5월 인텔 아이비브릿지 출시
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Limitation
Equipment
2013. 6월 인텔 하스웰 출시
Mu l ti pl e
G a t eMultiple Gate
Specification
Limitation
Equipment
What is ‘Tri-Gate’?
Even though GAA(Gate All Around) is the most ideal for transistors, it’s
difficult to produce in quantity due to processing. Tri-Gate on nano scale
is not only easier to produce, but also has similar properties with GAA.
Tri-Gate has great performance on gate control, but it need to resolve
some problems with short channel effect, hot carrier effect or series
resistance.
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Mu l ti pl e
G a t eMultiple Gate
Specification
About Spacer
Spacer is originated at the shave the film
of semicon. It makes the space between
the films to secure channel length of
transistor or the pressure of junction.
The properties we’re going to study on
- The trait changes with spacer
- The trait changes with the length
- Optimization of the best fin width
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Limitation
Equipment
Mu l ti pl e
G a t eMultiple Gate
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Specification
Limitation
Equipment
Mu l ti pl e
G a t eMultiple Gate
Specification
Vd • Vg, Stress
Limitation
Equipment
Channel Length, Width
Limitation
s
Temperature,
humidity or vibration
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The length and width
of Gate
Mu l ti pl e
G a t eMultiple Gate
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Specification
Limitation
Equipment
E q u i pme nt
Multiple Gate
Specification
<Probe Station>
 Use four probes.
 Apply voltage to all probes
and each probe measures
currents.
 Usually, it is better to use
SMU probe as Gate.
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Limitation
Equipment
<Parameter Analyzer>
It is possible to analysis the
properties of semiconductor
using B1500.
 It is required to observe
the monitor to check normal
operations.
E q u i pme nt
Multiple Gate
Specification
Limitation
Equipment
<Probe Station>
Top / Bottom
(micro)
Top / Bottom
Right / left
the front / the rear
※Tip
After contacting on device, it is
possible to move with only adjustment
of microscope.
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Adjustmen
t of right
and left
Adjustment
of the front
and the
rear
E q u i pme nt
Multiple Gate
Specification
Limitation
Equipment
<Probe
Station>
Right/left on
Wafer Chuck
 Apply voltage using B1500 and
measure it.
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E q u i pme nt
Multiple Gate
<1>
Specification
Limitation
Equipment
<2>
 1 equipment is called Fiber Optic and provides the light
when measurements.
 2 equipment fastens the device and probe holder.
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E q u i pme nt
Multiple Gate
Specification
Limitation
Equipment
C-V Equipment for measurement
3. Start
2.Range of temperature
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1.Power
02) Body
L D D St r u c t u r e
Explanation
Measurement
Doping without spacer
R=(ρ*L)/A
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Doping with spacer
GIDL(Gate Induced Drain Leakage)
Explanation
Measurement
VG=-1.5V
VS
Oxide
Source(
VD=1V
GATE
n+)
Drain(
h
Electricfield
P-Si
VB
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e
n+)
Vt decrease due to Body
effect
DIBL(Drain Induced Barrier Lowering)
Explanation
Measurement
On condition of transistor :
VG >Vt
DIBL is the phenomenon that
Vt decrease due to lowering
of energy barrier.
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Hot Carrier
Explanation
Measurement
Hot Carrier
is( VG >Vt :inversion condition )
the phenomenon that electric
field from drain to source
increases because the
increment of Vd shorten the
length of channel.
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Hot Carrier
Explanation
Measurement
Vt increases because
elections in oxide are
trapped due to hot
carrier.
VG >Vt
VS
Source(
VD ↑
GATE
Oxide
Channel
n+)
P-Si
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e e
ElectricDrain(
field
n+)
I d s wi t h V g s
Explanation
Measurement
Ids with Vgs
GIDL
At Long channel, Vgs∝Id
∴Ids,v=1 > Ids,v=0.05
Leakage current
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Ids with Channel Length
Explanation
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Measurement
I d s w i t h S pa c e r
Explanation
Measurement
When the device doesn’t have spacer, the
Current is larger.
When the device has spacer, Ids decreases
Because series resistance increases.
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DIBL measurement
Explanation
Measurement
At 10nA,
Vgs difference = DIBL
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DIBL with Length and Width
Explanation
LD=70nm(Width)
LE=50nm(Width)
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Measurement
S u b - t h r e s h 0 l d s l o p e Sw i n g
Explanation
 d (log10 Ids )

S  

dV
GS


1
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Measurement
C dm
kT

ln(
10 )(1 
)
q
C oxe
Hot Carrier measurement
Explanation
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Measurement
Hot Carrier (L=250nm, W=70nm)
Explanation
Measurement
We can find that Id decreases
and Vt increases due to stress.
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Hot Carrier (L=250nm, W=70nm)
Explanation
Measurement
Ids  Ids
Current 
Ids
Ids decrease due
to aging of the
device as time
goes by.
Gate Voltage
1.5 V
Drain Voltage
3.0 V
Time
1min, 5min, 10min, 20min,
30min, 40min, 50min, 60min
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H o t C a r r i e r St r e s s m e a s u re m e n t ( 1 )
Explanation
Measurement
Gate Voltage
1.5 V
Drain Voltage
3.0 V
Time
1min, 5min, 10min, 20min, 30min,
40min, 50min, 60min
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H o t C a r r i e r St r e s s m e a s u re m e n t ( 2 )
Explanation
Measurement
Gate Voltage
0.8 V
Drain Voltage
1.6 V
Time
1min, 5min, 10min, 20min, 30min,
40min, 50min, 60min
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S e r i e s Re s i s t a n c e ( 1 ) - T h e o r y
Explanation
Measurement
Step for
Rsd
1) g m 
dI d
dVg
2) Y-function
= / 
3) β=slope2/Vd
Vg

Slope=Rsd
β=slope2/Vd
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S e r i e s Re s i s t a n c e ( 2 ) w i t h s pa c e r
Explanation
Measurement
Width
Rsd(Spacer)
Rsd
55nm
761Ω
650Ω
70nm
478Ω
190Ω
① When the device has spacer, Rsd increases due to n- doping of
LDD structure.
② Rsd increases with the decrease of surface area as width decrease.
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S e r i e s Re s i s t a n c e ( 4 ) w i t h c r y s t a l d i re c t i o n
Explanation
Measurement
(100)
(110)
Si 원자 수
↓
↑
Scattering
↓
↑
① W↑ A↑
이동도
↑
↓
② 
On Current
↑
↓
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1
u
∴ R↓
∴ u(100) > u(110)
R(100) < r(110)
S e r i e s Re s i s t a n c e ( 5 ) w i t h c r y s t a l d i re c t i o n
Explanation
Measurement
① It is measured that Rsd decrease as channel width increase
because surface area increase.
② It is measured that Rsd decrease as the degree of crystal direction
increase because the current is large.
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03. Remarks
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E va l u a t i o n St a n d a r d
Evaluation items
1. How many the devices we use
2. A change of the current as Stress
3. The number of experiments
4. The understanding of measurements
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Standard
Points
Over 21
5
18 - 20
3
Under 17
1
Under 3%
5
Under 5%
3
Under 10%
1
Over 6
5
3- 5
3
Under 2
1
Can explain very well
5
Can explain in some degree
3
Can hardly explain
1
Total
16/20
Achievement
Used over 28
Got about
6.25%
Have done 6
Studied a lot.
80%
E va l u a t i o n St a n d a r d – i n d e t a i l
1. How many devices we used?
- We’ve used kinds of the devices such as LD, LE, AR and JM as channel length(90nm,
100nm, 130nm, 150nm, 180nm, 250nm, 500nm)
Therefore, the sum of the devices we’ve used is 28 which is 4 times 7.
2. A Change of Current as Stress
-
Generally, a current tends to change as variables. When we consider stress as the
only variable and compare before stress with after stress, then we get the change
of Gate voltage which is about 0.05V to 0.1V. It’s 6.26% compared to 0.8V.
3. The number of experiments
-
We’ve measured ①the properties of Id-Vg, ②DIBL, ③Sub-threshold Swing, ④
GIDL, ⑤Hot Carrier Stress and ⑥Series Resistance. Therefore, it’s 6 in total.
4. The Understanding
- All members in our team have done one’s parts, and we always studied together
before we start new measurements. Therefore, we think we’re knowledgeable
about our topics.
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Schedule Plan
March
April
May
June
July
August
Select a topic
Study for
equipments
measurement
for basic
DIBL,GIDL
measurement
Hot Carrier
Effect
Simulation
Measure SCE
Specify a
thesis
Work for a
thesis and
examine
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:
:
:
:
proceeded as a plan (100%)
has been a little change (90%)
didn’t proceed as a plan (60%)
hasn’t proceeded yet
( - )
Schedule Plan – in detail
1. Select topic : As we planned, we had considered our topic for two
2.
3.
4.
5.
6.
7.
weeks with our professor and graduate student. (100%)
Study for Equipment: Since the middle of March, we’d started to study
our equipments and run ourselves. (100%)
Measurement for Basic: Before we work on our graduation thesis, we
needed knowledge for the basic properties of semiconductors, so we
spent about two weeks, working on basic such as the properties of IdVg or Vt. (100%)
DIBL, GIDL Measurement: We measured DIBL, GIDL but it took a
little longer than we expected. We spent about a month to get the
results of these. The main reason was that our device is too old to show
its proper properties. (90%)
Hot Carrier Effect: Even though 4th took a little longer, we kept 5th
week’s plan. (100%)
Measure SCE: Originally, SCE was supposed to measure during first two
months. Because we finished measurements for DIBL and GIDL , so we
had to move on the next step. (60%)
Specify a thesis: here is our current step, and every measurements for
our thesis have done. We’re going to work on composition for a thesis
after this final presentation. (100%)
Total : 92.86%
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Abstract
Spacer의 유무에 따른 Vg-Ids측정을 통하여 소자의 특성을 비교하였다.
첫째, L(100nm,130nm,180nm,250nm,500nm)별로 Vg-Ids 측정결과 L가 짧아질수
록, Spacer가 없는 경우에 전류가 많이 흐르는걸 볼 수 있었다.
둘째, L,W에 따라 DIBL(Drain Induced Barrier Lowreing)을 측정한 결과 L이 클수
록 Width가 짧을수록 DIBL이 작게 나타나는 걸 볼 수 있었다. 또한 L가 짧을수록
SS(Subthreshold Slope)가 크게 나타남을 확인 할 수 있다.
셋째, Spacer의 유무에 따른 Hot-Carrier와 Rsd(시리즈저항)을 측정 한 결과
Spacer가 있는 경우 Hot-Carrier열화 정도가 작게 나타나고 Rsd는 크게 나타났다.
넷째, 결정방향(100,110)에 따른 Drain Current 측정 결과 결정방향 100(45도)에
서 큰 걸 알 수 있었다. 즉, 결정방향 100(45도)에서 Rsd가 작게 나타난다.
Wo r k D i v i s i o n
Division of a
Work
Sung In, Jung
1. Research materials
2. Analysis the change of
properties as spacer
3. Composition of a thesis
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Geon Woo, Baek
Gi Yeon, Kim
1. Analysis the properties
of measurements
2. Proof or Give feedback
for a thesis
3. Get references
1. Work on simulation
2. Analysis the best fin
width
3. Composition of a thesis
Re f e r e n c e s
• 논문 <소자 레이아웃이 n-채널 MuGFET 의 특성에 미치는 영향>,
이승민 외 3명
• 논문 <Pi-Gate SOI MOSFET>, Jong-Tae Park 외 3명
• 반도체소자공학, Pierret 저, 교보문고,1997
• http://www.kipo.go.kr/kpo/ (SPACER 관련자료)
• http://www.naver.com/ (MuGFET 관련자료)
• https://www.google.co.kr (첨부사진)
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THANK YOU
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