Transcript Design Space Exploration of Hardware Virtual Machines for

TD5102 Embedded System
in Silicon
FPGA Architecture and EDA
Dr. Ha Yajun
(E1-08-17, [email protected])
http://courses.nus.edu.sg/course/elehy/TD5102/
© NUS 2005
Embedded Systems
An embedded system is nearly any computing system
(other than a general-purpose computer) with the
following characteristics
Single-functioned
Typically, is designed to perform predefined function
 Tightly constrained
Tuned for low cost
Single-to-fewer components based
Performs functions fast enough
Consumes minimum power
 Reactive and real-time
Must continually monitor the desired environment and react to
changes
 Hardware and software co-existence

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Embedded Systems
Examples:
Communication devices
Wired and wireless routers and switches
 Automotive applications
Braking systems, traction control, airbag release systems, and
cruise-control applications
 Aerospace applications
Flight-control systems, engine controllers, auto-pilots and
passenger in-flight entertainment systems
 Defense systems
Radar systems, fighter aircraft flight-control systems, radio
systems, and missile guidance systems

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Simplified and General Embedded
System Design Methodology
Algorithm
Functional
Modeling
Algorithms
Problem Partitioning
Software Func.
Model
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Hardware
Func. Model
Software Development
Architectural synthesis
Application Source
Code
Structural RTL HDL
Processors
Application Specific
Hardware(ASIC/FPGA)
Platforms
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SW/HW
Interface
SW/HW
Interface
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Three Kinds of Embedded System
Implementation Platform Choices
Processor
Reconfigurable FPGA
+
Rf +|-|*|>|
D$
-
>
*
Hardwired
ASIC
+
-
* >
ID
Sw
I$
Sw
Configuration
+
* >
Programmable
Sequential
Instruction flow (cycle)
Transfer bottleneck
Power:
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Configurable
No wiring
Parallel wired algorithm
No configuration
“Program” flow (occasionally) Overhead
Distributed data
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Why Use Reconfigurable Hardware?
Processor
Processor- ProcessorASIC
FPGA
Performance
Low
High
Flexibility
High
Low
Power
High
Low
Medium
High
Medium
Why FPGAs ?
•
•
•
•
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Combine flexibility with performance.
Shorter time-to-market and longer time-in-market.
#FPGA gates/USD: 2004 1 M/10$.
FPGA capacity: now 2004 50Mgates
=> FPGAs get used as functional part of a design (<-> prototyping)
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Integration in System Design
Integration of Functions
Embedded Software Tools
CPU
CPU
Embedded Software Tools
Embedded Software Tools
FPGA
I/O
FPGA +
Memory + IP +
High Speed IO
(4K & Virtex)
Logic Design Tools
Memory
Logic + Memory
+ IP +
Processors +
RocketIO
(Virtex-II Pro)
Logic Design Tools
Programmable Systems
usher in a new era of system
design integration
possibilities
Logic Design Tools
Time
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FPGA Based Reconfigurable Platform
 Reconfigurable Platforms Architectures
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EDA for Reconfigurable Architectures
Applications of Reconfigurable Platforms
Lab Sessions on FPGA Board
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Simplified FPGA Architecture
Functional
Block
I/O Block
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All the three components can
be re-programmed with
configurations to implement
application-specific digital
circuits.
Routing
Network
For example, each functional
block can be programmed to
implement a small amount of
digital logic of a design; the
routing network can be
programmed to implement
the design specific
interconnection pattern; I/O
blocks can be programmed
to implement the input and
output ports according to
design requirements.
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FPGA Reconfiguration
Time 1
Bitstream
File 1
Time 2
Bitstream
File 2
All the programming information for the three programmable RA
components is stored in a configuration file. The configuration file
for a RA is often called a bitstream compared to a binary executable
for a processor. Once a bitstream for a digital logic design is
downloaded to a RA, the RA is programmed to implement the
design. By providing different bitstreams, a single RA can be reprogrammed to implement different designs at different times.
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FPGA Functional Block
Local
Interconnect
LE
LE
Functional Block
Outputs
…..
Functional Block
Inputs
LE
Functional Block Internals
Our target RAs use the Look-Up Table (LUT) type of functional block.
Such a functional block is normally made of one or several logic
elements (LE). They differentiate from each other mainly in terms of the
input size of a LE and the number of LEs in a functional block. State-ofthe-art RAs normally use 4-input LEs.
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FPGA Logic Element
LE Internals
The LE consists of a 16 SRAM cell Look-Up Table (LUT), and a flip flop
(FF). The 16 SRAM cells LUT stores the truth table of any 4-input logic
function, thus it can implement any 4-input logic function. The FF
implements the storage element in a sequential circuit.
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LUT Content
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A
B
C
D
F
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
1
0
1
0
0
0
0
1
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0
0
1
1
0
0
0
1
1
1
1
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
1
1
1
0
0
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1
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A
B
C
D
F
F = A*B+C*D
The 16 SRAM cell LUT stores the output column
of the truth table of the F function. The 4 inputs
A, B, C and D will determine which bit the F
value is for the current values of A, B, C and D.
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Additional Computational Resources
Memory blocks
• Besides the LEs present in
previous slide, some functional
blocks in different target RAs
have architecture specific
features to improve the
performance when implementing
arithmetic functions.
• These architecture specific
features include carry logic,
embedded memory blocks,
multiplier and other hard cores.
Microprocessor blocks
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• Hard cores generally
implement functions efficiently
compared to FPGA functional
blocks.
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FPGA Routing Architecture
A logic block input or output pin can connect to some or all of the wiring segments in
the channel adjacent to it via a connection block of programmable switches. At every
intersection of a horizontal channel and a vertical channel, there is a switch block. It is
a set of programmable switches that allow some of the wire segments incident to the
switch block to be connected to others. By turning on the appropriate switches, short
wire segments can be connected together to form longer connections.
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FPGA Routing Wires
• Some target RAs contain
routing architectures that
include different lengths of
wires.
• The length of a wire is
the number of functional
blocks it spans.
• Left figures show wires of
length 1, 2 and 4.
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XC4000 Routing Architecture Example
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Commercial FPGA Architecture Comparison
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PowerPC-based Embedded Design
RocketIO
Dedicated Hard IP
DSOCM
BRAM
PowerPC
405 Core
Off-Chip
Memory
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OPB
Processor Local Bus
Hi-Speed
Peripheral
e.g.
Memory
Controller
ZBT SRAM
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DCR Bus
Data
PLB
Flexible Soft IP
GB
E-Net
DDR SDRAM
IBM CoreConnect™
on-chip bus standard
PLB, OPB, and DCR
Bus
On-Chip Peripheral Bus
Bridge
UART
SDRAM
GPIO
Arbiter
Arbiter
Instruction
ISOCM
BRAM
On-Chip
Peripheral
Full system customization to meet
performance, functionality, and
cost goals
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MicroBlaze-based Embedded Design
Local Memory
MicroBlaze
Bus
32-Bit RISC Core
LocalLink™
FIFO Channels
0,1…….32
Custom
Functions
Arbiter
D-Cache
BRAM
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Instruction
Bus
Processor Local Bus
Bridge
Hi-Speed
Peripheral
10/100
E-Net
Data
PLB
On-Chip Peripheral Bus
UART
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Configurable
Sizes
Possible in Dedicated Hard IP
PowerPC
Virtex-II Pro
405 Core
OPB
Custom
Functions
Off-Chip
Memory
Flexible Soft IP
e.g.
Memory
Controller
Arbiter
BRAM
I-Cache
BRAM
GB
E-Net
On-Chip
Peripheral
FLASH/SRAM
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FPGA Based Reconfigurable Platform
 Reconfigurable Platforms Architectures
EDA for Reconfigurable Architectures


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Applications of Reconfigurable Platforms
Lab Sessions on FPGA Board
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FPGA Design Flow
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Time Profile for Design Flow Steps
Logic Optimization and routing steps normally
consume the major part of the design flow time.
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FPGA Technology Mapping
Technology step restructures the primitive logic
gates, generated from the logic optimization step,
into sets of 4-input functional blocks.
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FPGA Placement and Routing
The placement step finds physical locations for
functional blocks, while the routing step finds physical
routes for logic connections.
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Embedded Design in an FPGA
Embedded design in an FPGA consists of the following:

FPGA hardware design

C drivers for hardware

Software design
RTOS versus Main + ISR
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Embedded Development
Tool Flow Overview
Standard Embedded SW
Development Flow
Standard FPGA HW
Development Flow
C Code
VHDL/Verilog
Compiler/Linker
Synthesizer
(Simulator)
Simulator
Object Code
Place & Route
?
?
CPU code in
off-chip
memory
CPU code in
on-chip
memory
Download to FPGA
Download to Board & FPGA
Debugger
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Embedded Development Kit
The Embedded Development Kit (EDK) consists of the
following:

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Xilinx Platform Studio – XPS
Base System Builder – BSB
Create and Import Peripheral Wizard
Hardware generation tool – PlatGen
Library generation tool – LibGen
Simulation generation tool – SimGen
GNU software development tools
System verification tool – XMD
Virtual Platform generation tool - VPgen
Software Development Kit (Eclipse)
Processor IP
Drivers for IP
Documentation
Use the GUI or the shell command tool to run EDK
Detailed data sheet of Xilinx FPGA devices and user manuals of ISE
and EDK tools are available online at
http://www.xilinx.com/support/library.htm
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FPGA Based Reconfigurable Platform
 Reconfigurable Platforms Architectures
 EDA for Reconfigurable Architectures
Applications of Reconfigurable Platforms

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Lab Sessions on FPGA Board
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Why Networked Hardware?
--- Quoted from Cindy’s Boy Friend!!!
Cindy Crawford asked me to
encrypt our mobile phone
talk!!! It is not an easy job!!!
So I resort to hardware.
But one day Cindy cried and told
me that our talk had been
disclosed. I laughed and said
“Baby, never mind, I will change
the encryption instantly through
the network!!!”
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Future Networked Applications Need Client
Platforms with Flexible Hardware Acceleration
 Future
networked applications can require high
computing power up to 1000 Giga Ops [Nakatsuka,
ISSCC’99], thus hardware acceleration is generally
needed, and networked applications will contain both
software and hardware components.
 Different
networked applications may use different
industry standards to support new services, and
require the client platforms to be flexible.
 Networked
applications usually work with a serverclient model, and require the client platforms to be
connected to the network.
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Target Client Platform:
Networked Reconfigurable Platform
Application
Description
HW
Part
SW Part
ISP1 ISP2
Dowloading
ISPN
static interconnect network
ASIC
Distr.
memory
arch.
Reconfigurable
Hardware
Both ISP and reconfigurable HW can be programmed to
flexible!
adapt changing standards.
 Reconfigurable HW can provide a better than ISP
energy efficiency of high processing power vs. power
consumption.
High computing power!
 Configurations for both ISP and reconfigurable HW can
networked!
be network downloaded.

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Commercial FPGA Platform
Up to 16 serial transceivers
HW
Part
SW Part
ISP1 ISP2
Dowloading
PowerPCs
Application
Description
ISPN
static interconnect network
ASIC
Distr.
memory
arch.
Reconfigurable
Hardware
ReConfig.
logic
Both ISP and reconfigurable HW can be programmed to
flexible!
adapt changing standards.
 Reconfigurable HW can provide a better than ISP
energyofefficiency
Courtesy
Xilinx (VirtexofII high
Pro) processing power vs. power
consumption.
High computing power!
 Configurations for both ISP and reconfigurable HW can
networked!
be network downloaded.

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Networked SW/HW Reconfiguration of
Networked Information Appliance
Advertise App
on Web Page
User
Selects
App
User
Download
s App
Web Page
Description
ISP1
Dowloading
HW
File
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ISPN
static interconnect network
ASIC
Java File
ISP2
Distr.
memory
arch.
Re-configurable
Hardware
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Web MPEG Video Player
Java MPEG Player
+
IDCT bitstream
Server Side
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CPU
+
FPGA
Client
Web Page
Client Side
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Networked Reconfiguration is Better
Service
Provider
Service Request
Service
Client
network
Service II
Data
Streams
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Service II
Service I
Reconfig …...
Data
Info
Streams
Service I
Reconfig
Info
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FPGA Based Reconfigurable Platform
 Reconfigurable Platforms Architectures
 EDA for Reconfigurable Architectures
 Applications of Reconfigurable Platforms
Lab Sessions on FPGA Board
 Lab Session 1: Reconfigurable fabric based hardware design
 Lab Session 2: Processor+Reconfig Fabric based system design
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MEMEC Virtex-4 LC FPGA Board
Serial Port
FPGA
Push Buttons
DIP Switches
LEDs
More FPGA board related documentations have been put online at
http://courses.nus.edu.sg/course/elehy/EE4218/projects.htm
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FPGA Board Demo
7-segment Display
When PUSH2 (SW5) is not held
down, the 7-segment display (DD1)
does a binary-to-hex conversion of
the binary number represented by
the 4-bit DIP switch (SW3).

When PUSH2 (SW5) is held
down, the 7-segment display (DD1)
counts from 0-9.

SW5
PUSH2
LED1, LED2, LED3, and LED4
count in binary from 0-9 (matching
what is on DD1 when PUSH2 is
pressed).

Pushing PUSH1 resets the
counter.

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FPGA Lab 1 & 2
 Please
 Watch
print relevant docs by yourself and bring to labs!
the FPGA board demo closely
 Lab
1: Try to re-implement the demo with Xilinx ISE on
your FPGA board and do the assignment

Design files for the demo will be installed on your PC.

You need to use Xilinx ISE tool to generate and download
the bitstream.

Get familiar with Xilinx ISE environment and link the
various FPGA design flow steps to the tool.

Browse and understand the design files for the demo.
 Lab
2: Follow the Xilinx EDK tutorial that can be found
in the TD5102 course web site under project page.
Lab session in Signal Processing and VLSI Lab (E4-08-34)
2:00-5:00pm on 13 & 14 Dec!
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Summary
 FPGA architectures
 EDA
have been introduced.
tools for FPGAs have been introduced.
 Applications
of FPGA for networked platforms have
been introduced.
 Lab
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introduction.
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