Transcript A Debug Probe for Concurrently Debugging Multiple Embedded

Presenter : Shao-Cheih Hou
Sight count : 11
ASPDAC ‘08
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More and more IP connect on bus in SoC
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Single bus is not efficiency
Full connect is too complex and high cost
Network is a good way for chip(NoC)
In NoC, too many IPs need to verification
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Design for debug => debug platform
Debug need more flexible
。Event trigger
。Trace
。Run stop
。Debug prob
Tracing[1,3,
12,13,22]
Coresight[4]
JTAG[21]
DfD for
embedded
cores[4]
Silicon
debug
platform
Internal
nodes[21]
Open Core
peotocol[15]
Debug
method
This paper
interface
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Debug prob
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Access module
Core debug module
Core trace module
Transaction trace module
DP programming module