Transcript A Debug Probe for Concurrently Debugging Multiple Embedded

Presenter : Shao-Cheih Hou
Sight count : 11
ASPDAC ‘08
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Existing SoC debug techniques mainly target busbased systems. They are not readily applicable to the
emerging system that use Networkon-Chip (NoC) as
on-chip communication scheme. In this paper, we
present the detailed design of a novel debug probe
(DP) inserted between the core under debug (CUD)
and the NoC. With embedded configurable triggers,
delay control and timestamping mechanism, the
proposed DP is very effective for inter-core
transaction analysis as well as controlling embedded
cores’ debug processes. Experimental results show
the functionalities of the proposed DP and its area
overhead1.
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More and more IP connect on bus in SoC
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Single bus is not efficiency
Full connect is too complex and high cost
Network is a good way for chip(NoC)
In NoC, too many IPs need to verification
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Design for debug => debug platform
Debug need more flexible
。Programmable trigger
。Trace (timestamping)
。Delay control
。Run stop
。Debug prob
Tracing[1,3,
12,13,22]
Coresight[4]
JTAG[21]
Internal
nodes[21]
Monitor for
NoC[7,8]
DfD for
embedded
cores[4]
Silicon
debug
platform
Open Core
peotocol[15]
Debug
method
This paper
interface
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Debug software
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Software control
Each core structure config
Driver match
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On-chip debug architecture
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DA(debug agent)
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DP(debug probe)
Off-chip debug controller
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OCP and JTAG interface
Command I/O
Data output
DA (Debug Agent)
Receive/send debug command/data from/to Off-chip
Debug Controller by using system JTAG port
• Change debug command to package form, and passing to
specific CUD or DP
• Receive package form network and change to debug data
6
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Connect to Network interface(NI)
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OCP protocol (slave interface)
Memory-map for each DP
Control the delay of the debug probe
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For data synchronize
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JTAG Interface
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Another way to configure the delay control
ARM ICE JTAG protocol use in this paper
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Dump trace data from core by bus
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Solve “many-to-one”
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Time slot for each core under debug
Trace bandwidth : TD(i)~Bchip(TS((𝑁 − 1)/𝑁)
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Trigger Unit
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Control for config
Detector as comparator
MUX for output record
Record format
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Trace Unit
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Trace after trigger
Shadow buffer for start cycle
Record package
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The method for DP setup and run
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Environment setup
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ARM EICE JTAG
OCP protocol
Function Test – delay R/W
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Function Test – Transaction operation
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Area of DP
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The paper propose a debug platform
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For complex NoC base
Bus config and JTAG parallel
Trace for both core information and protocol information
Reconfigurable HW
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Similar as problem in my target
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NoC(not bus system) debug
Memory interface signal trace
JTAG and interconnect debug parallel
Problem for this paper
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Only the simulation, no real case
Area analyze only for DP, not all the platform
No detail for SW and off-chip debug controller