Transcript Document

Integrated Design, Debug and Test
Methodology to Meet Today’s
Time-to-Market Challenges
Dr. Graham J. Siddall
Chairman and CEO
Credence Systems Corporation
Agenda
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Semiconductor Market Trends
Time-to-Market Challenges
Design-to-Test Methodologies
Design, Debug and Diagnostics
Summary
Strengthening Worldwide Economy
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Economic stimulation from US
tax cuts
Improved consumer spending
Slowly depreciating dollar
GDP growth peaks in Q1 2004
IC Industry 2003/2004 : A Phased Recovery
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Recovery underway
- Cell phones recovery
underway
- PC market shows signs of
strength
Continued recovery depends
upon
- 3G cell phone adoption
- Corporate PC replacement
cycle
- General improvement in
electronics industry –
particularly communications
1H’03
2H’03
1H’04
2H’04
Spending
Consumer
Corporate

Cell Phones
?
PCs

Comms
IC Industry 2003/2004 : Beginning of Next Cycle
300,000
$252B
+21.8%
250,000
$224B
$252B
+5.6%
$207B
+23.1%
200,000
$ Millions
$239B
-5.2%
$152B
-32.2%
$155B
+1.9%
2001
2002
$168B
+8.3%
150,000
100,000
50,000
0
2000
2003
2004
2005
2006
Data Processing Electronics
Military/Civil Aerospace Electronics
Communications Electronics
Industrial Electronics
Consumer Electronics
Automotive Electronics
Source: Gartner Dataquest 2003-May
2007
IC Unit Recovery
Unit volume 20% greater thru May 2004 compared to 2000
Time-to-Market Pressures
 Penetration rates are increasing
 First-to-market advantage is more apparent
Source: Semico Research
Time-to-Market Pressures
Worldwide Mobile Hand Sets
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Rapid adoption and maturity of technology
Three year life cycles
Source: MIC, Sept 2003
Complex Designs with Increased Integration
Acceleration in number of transistors per generation of microprocessors
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Source: Intel Developers Conference 2002
Acceleration in complexity
Two year technology cycles
Problems Found On First Spin ICs/ASICs
Other
Firmware
IR Drop
Fast Paths
Slow Paths
Power
Mixed Signal
Reliability
Clock
Signal
Analog
45
40
35
30
25
Percent Failures
20
15
10
5
0
Logic
First Spin Problems
Overall 61% of New ICs/ASICs Require At Least One Re-Spin
Source: Aart de Geus, Chairman & CEO of Synopsys, 2003 Boston SNUG keynote address
Economic Implications of Design Problems
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Leading
edge devices carry
.
huge risks in time to market
SoC devices must have high
performance, low cost and high
yield
Expensive mistakes
 Intel Pentium FDIV bug - caused massive returns of millions of
shipped Pentium processors
 Nvidia – suffered delayed product shipments due to poor yield on
new 0.13 micron design and opened market to competition
 Bluetooth – still missing the market window due to complexity, yield
problems, process variations
Traditional Design-to-Test Methodology
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Designers have traditionally been unaware of test and debug trade-offs
and implications
Poor/slow flow of information from test to design
Inefficient flow of information from design to debug/validation and back
Organizational and functional boundaries exist between design,
validation probing and test, and production test
Many Designer’s View of the World
T0
T1
T2
T3
T4
T5 T6 T7 T8
T9
Tn…
Product Definition
Product Planning
Product Design
Debug, validation, certification,
and ramp production
Debug, etc. are small, minor
steps to getting the product out
of design and into production.
Volume Production
End of Life
The Reality…
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
Tn…
Product Definition
Product Planning
Product Design
Proto/1st Article
Products…
- don’t work right
- don’t meet specs
- get stalled in debug
- get delayed in validation
- delay getting into production
- delay getting into volume
Debug/Validation
Qual/Certification
Ramp Production
Volume Production
End of Life
Design Characterization
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Even if there are no significant functional bugs, product performance
(e.g. speed, yield) is often below target
How does the design perform over the range of:
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Process Variation
Temperature
VCC Specs
Timing Specs
Electrical
Spec
Range
100% Yield to
Design Specs
Temperature Range
Process Variation
Strategy
Integrated Design-to-Test Methodology
Shorten product design
lifecycles
Reduce time-to-market
Minimize number of mask sets
Reduce cost of redesign
Solutions
Design
Debug & FA
Identify and locate critical
device timing errors
Increase confidence into
production
Maximize yield of high ASP
devices
Engineering
Validation Test
Provide fastest path to HVM
and feedback yield data to
FA
Provide lowest cost-of-test
Production Test
Shorten Time-to-Market – Maximize Profit Window
Integrated Design-to-Test Methodology
Engineering Validation Test Flow
Automatic
Test Program
Development
Test Program
Debug
Prototype
First Silicon OR
FA Sample
EDA
Design for Test
Strategy
EGSoft Navigation
Engineering
Test Results
Probing Strategy
Engineering
Probe Results
Integrated design debug / validation environment ensures fast and accurate
fault isolation and characterization
New Photon Probing Technology
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Physics: Accelerated by an E-field, charge carriers during a switching
event emit photons
Signal: Photons are detected through the bulk Silicon and “binned” in
time slots
Completely passive and non invasive measurement
Diagnostic Benefits of New Design-to-Test Methodology
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Characterization of critical timing
paths at node level
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Improve speed performance
Address contentions, clock skews,
race conditions
Fast and interactive process for
fault localization and
characterization
Localized resistive failures – can’t
be done through pinned out
information
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Example: Resistive Via
Example: Electromigration
Backside Imaging and Measuring Delay Propagation
Inverter chain .13mm 1.2V
INV1
INV2
200psec
INV3
INV4
INV5
INV6
INV7
0.13 mm inverter chain image
0.2 mm resolution
100X 120x90 mm FOV
Economic Benefits of New Design-to-Test Methodology
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Fastest time-to-market
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Achieve most profit in first six months of a device introduction
Reduced number of mask spins
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Save expensive mask sets
Rapid feedback to design engineers to optimize for speed bins
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Maximize high margin devices
Estimated margin impact:
Chipsets
Estimated margin impact:
Micro-Processors
Effective debug/validation
(1% improvement in speed
bin or yield over lifetime)
$700K
$10,000K
No Mask Respin
(50% of mask set)
$88K
$350K
Improved time to market
(Incremental $ per week)
$500K
$5,000K
Impact
Benefit
Conclusion
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New device designs are increasing in complexity
Rapid device introduction is critical for profitability
An integrated engineering debug and validation feedback loop
can cut device time to market and improve device profitability
It is quite rare for a product to be bug-free.
Validating and debugging a product quickly can often make the
difference in profitability for that product.
Even if there are no significant functional bugs, product
performance (e.g. speed, yield) is often below target