Transcript Design of a Reusable SpaceWire Link Interface for Space

Design of a Reusable
SpaceWire Link Interface for
Space Avionics and
Instrumentation
Mark A. Johnson
Senior Research Engineer
Southwest Research Institute
San Antonio, Texas
(210) 522-3419
[email protected]
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Space LAN Background
• Spacecraft Local Area Networks (LANs)
– Not a new concept. MIL-STD-1553B is a common
spacecraft data network that is used throughout the
spacecraft community
– Recent interest in high performance LANS is fueled by the
promise of:
• Enabling technology for distributed data collection and processing
(I.e. multi-instrument clusters or “Sensor webs”)
• Reduced I&T time and cost
• Leverages off of developments and successes in commercial industry
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SpaceWire Overview
• What is SpaceWire?
– High performance serial bus supporting rates between 2Mbps and
400Mbps
– Based on IEEE 1355-1995, coupled with LVDS physical interface
– European Space Agency Standard - ECSS-E-50-12A
– Layered Protocol (Physical, Signal, Character, Exchange, Packet,
Network)
• Goals of Spacewire
– Provide a unified high speed data handling infrastructure that will
meet the needs of future, high bandwidth space missions
– Reduce system integration costs
– Promote compatibility between instruments and subsystems
– Encourage design reuse across missions
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SwRI SpaceWire IR&D Program
• Major goals of SwRI SpaceWire IR&D program.
– Develop a re-usable HDL (Verilog or VHDL) based SpaceWire Link
Interface Core
• Motivating factor is to provide a low-power, reusable, and portable logic
core that can be easily incorporated into FPGA designs without requiring
separate SpaceWire interface IC’s.
– Optimized for size and board area constrained electronics (i.e. miniaturized
science instruments, Command and Data Handling systems, etc.)
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SwRI SpaceWire IR&D Program
• Major Goals of IR&D Program - Continued
– Provide a test bed to evaluate the applicability of Internet Protocol (IP) to
the SpaceWire Serial Bus Protocol.
Application
Layer
Presentation
Layer
Application
Layer
Session Layer
Transport
Layer
Transport
Layer
Network Level
Network Layer
Internet Layer
Packet Level
Network
Access Layer
Exchange
Level
Character
Level
Data Link
Layer
Physical Layer
ISO OSI Layer Model
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Physical Level
TCP / IP Model
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SpaceWire Layer Model
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Spacewire Technical Overview
• Spacewire standard defines a multi-level interface
– Physical level
• Connectors, cables, board impedances, etc.
– Signal level
• Electrical characteristics, signal levels, timing
– Character level
• Defines how data and control characters are encoded
– Exchange level (or link level)
• Defines the way the Spacewire link operates. Covers initialization, normal operation,
error handling
– Packet level
• Defines the way data is encapsulated in packets for transfer
– Network Level
• Defines the structure and operation of a Spacewire network, including routing,
architecture, etc.
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Spacewire Technical Overview
Signal Level
• Spacewire link comprises 2 pairs of differential signals
– Transmit Data / Strobe
– Receive Data / Strobe
• Spacewire uses Data-Strobe (DS) encoding
– Encodes transmit clock with data into Data and Strobe
– Clock is recovered by XORing the Data and Strobe
together
– Provides skew tolerance of almost 1 full bit time
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Spacewire Technical Overview
Character Level
• Based on IEEE 1355-1995, with
extensions to support Time Code
broadcast.
– Two Types of Spacewire “characters”:
Data & Control.
– Data characters are 8 bits with data /
control flag = 0.
– Control characters have data / control flag
= 1. Used for link flow control and to
signal the occurrence of errors.
– All characters contain a parity bit that
ensures odd parity over.
– Null control character is sent whenever a
link is not sending data or control tokens
to keep the link active and support
disconnect detection.
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Spacewire Technical Overview
Character Level
• Character Types:
– Null = Esc / FCT: 8 bits
• Used in initialization / fill
– Flow Control Token (FCT): 4
bits
• Indicates to receiving node that
8 more bytes may be
transmitted
Parity Calculation and Coverage
– End of Packet (EOP): 4 bits
• Signifies end of normal packet
– Error End of Packet (EEP):
4 bits
• Signifies end of packet w/
error(s)
– Data: 10 bits
– Time Code = Esc / Data: 14
bits
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Spacewire Technical Overview
Exchange / Link Level
• Exchange Level (or Link Level) is
responsible for making a connection
across a link and for managing the flow
of data across the link.
• Exchange Level comprises 5 major
processes
– Initialization
– Flow Control
– Detection of Disconnect Errors
– Detection of Parity Errors
– Link Error Recovery
Link Interface Block Diagram
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Spacewire Technical Overview
Exchange / Link Level
Nominal Link Operation State Diagram
Link Error Handling
State Diagram
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SpaceWire Link Interface Module (SLIM)
• cPCI SpaceWire Link Interface
• Proof of concept module
developed as part of this IR&D
for the test, verification, and
operational experience with the
SpaceWire protocol
• Provides:
– Single Channel, full-duplex
SpaceWire Link Interface
– Fully Compliant CompactPCI
target interface
– 3U cPCI form-factor
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SLIM Overview
• SpaceWire Link is implemented
in a single Actel FPGA
16K x 9
16K x 9
FIFO
16K x 9
FIFO
16K x 9
FIFO
FIFO
16K x 9
16K x 9
FIFO
16K x 9
FIFO
16K x 9
FIFO
FIFO
6
6
– Actel 54SX72A
•
•
•
•
–
–
–
–
–
SEQ: 32.31%
COMB: 30.04%
In-house developed cPCI Core
Coded in Verilog
Spacewire Link Core
4 stacked 16x9 Rx FIFOs
4 stacked 16x9 Tx FIFOs
LVDS receiver
LVDS driver
All components chosen to have
direct flight equivalent
replacements.
9
8
9
FIFO Controller
and Read / Write
Logic
32
Interrupt
Processing
Logic
SwRI cPCI Target Core
cPCI / Spacewire Link
FPGA
33MHz, 32bit cPCI Bus
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Design Verification and Validation
• Two Tiered Verification Approach
– Simulation Test Bench
– Laboratory Testing
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Simulations
• Simulation test bench created from board
schematic
– Pre-layout RTL FPGA
– Post-layout back-annotated FPGA
– Model of companion SpaceWire block
– FIFO models w/ timing checks
– cPCI processor model w/ timing checks
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Simulations
SpaceWire Model
• SpaceWire Model provides:
– Transmit:
• Normal sequences of all types (control & data)
• Error sequences
– Receive:
• Reports control & data received
• Reports link error sequences received
– Loop-back mode: Tx wired to Rx
• Reports control & data transmitted
• Reports link error sequences transmitted
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Simulations
cPCI Model
• cPCI Model provides:
– Writes
– Reads w/ data compare checks
– Loop reads for specific data patterns
– I/O timing checks
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Laboratory Prototype Testing
• Test set configuration
– 4-Links SpaceWire card
for SpaceWire
• interface compatibility
testing
– COTS Single Board
Computer (SBC)
• Command, Control,
Stimulus
– VMETRO cPCI bus
Protocol Analyzer
• Monitoring of cPCI bus
for PCI protocol
violations
– Agilent Logic Analyzer
• Detailed timing
verification
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Laboratory Prototype Testing
• Laboratory Testing Results
– Link Operating Frequency – 2Mbps up to 30Mbps
– Successfully verified full SpaceWire Link operation
• Link Initialization, FCTs, restart, error handling, timing, variable length
packet transmission and reception, time code operation
– Successfully verified full cPCI target compliance
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