Transcript VHDL Synthesis for High

It’s Still an Analog World:
Signal and Power Integrity
2005 MAPLD International Conference
Washington, D.C.
September 6, 2005
2005 MAPLD
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Who am I?
• Shahana Aziz
– Senior Digital Designer (GSFC)
– Current Activity
• Hardware lead for JWST Integrated Science Instrument
Module C&DH system
– Expertise
• Signal integrity simulation for reliable PWB designs
– Focus
• Ensuring reliable PWB design in high performance digital
systems
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What do We Want to Accomplish?
• Deal (in depth) with a significant practical
aspect of design integrity (power and signal
integrity)
• Present concrete techniques for identifying
and mitigating signal and power integrity
issues
• Demonstrate tool operation (as time
permits)
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Agenda - It’s Still an Analog World
•
•
•
•
•
•
•
•
Introduction: What is Signal and Power Integrity?
Common Signal Integrity Considerations
Common Power Integrity Considerations
Guaranteeing the Design: Simulation Techniques
Simulation Examples
Comparison Examples
PCB Design Methodology
References
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Agenda – What is Signal and Power
Integrity?
• Examples of signal integrity problems
• Understanding the concerns
• Definition of critical signals
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What is Signal and Power Integrity? (cont.)
Peak voltage: ~3V
GND
1.7V
Maximum
undershoot: 1.7V
MFG Abmax is -.5V
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What is Signal and Power Integrity? (cont.)
Too much overshoot
3.8 V
Limit
• Significant and
Unacceptable Over and
Undershoot
-0.5 V
Limit
Too much undershoot
-0.5 V
Limit
From: Ed James, GSFC, ACE Signal Integrity Tuning
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What is Signal and Power Integrity? (cont.)
•
•
Is 1.5 or 1.25 volts of ground bounce
OK?
1.5 volts almost 1/2 way between a
logic “0” and “1” for 3.3 volt logic
High Slew
• Tfall = 1.5 ns
• Gnd Bounce = 0.4V
Low Slew
• Tfall = 6 ns
• Gnd Bounce = 0.1V
See: Actel SSO Signal Integrity. PDF, Simultaneously Switching Noise and Signal Integrity
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What is Signal and Power Integrity? (cont.)
1) Valid “Start” Cycle Pulse (Red)
2) When Data Bits drive low (Yellow),
ground bounces causing a phantom
positive glitch on “Start” locking up the
system
• Is every thing ok because the
ambient “Functional Test”
passed?
Purple - 3.3 V
0.5 V/div
Note more noise as AD driven “High”
Green - D Gnd
0.5 V/div
Note more noise as AD driven “Low”
Yellow - AD 12
2 V/div
Red – Start signal
0.5 V/div
Note signal is nominally driven
“low”, glitches represent internal
chip ground
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What is Signal and Power Integrity? (cont.)
• Signal Integrity ensures signals are of sufficient quality to reliably
transmit their required information, and do not cause problems to
themselves or to other components in the system.
• Signal Integrity applies to Digital, Analog and Power electronics
• Signal Integrity issues are more common now because electronics are
more dense and chips have faster rise times
– Assuring Signal Integrity now involves more knowledge of such
RF techniques as terminations, impedance matching
• Major function of engineering, next to conceiving the correct design, is
implementing the design correctly
• Signal integrity assures the circuit design operates as intended and
must be designed in.
– Correct design relies on experience, best practices, analysis and
simulation to ensure desired signal quality.
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Designing the System Correctly
• Fundamentally, signal integrity must be designed in and not
"discovered" by test.
– Tests verify that signals have the intended integrity.
– Tests are not designed to qualify a poor design
• Each designer identifies the critical signals and ensures their
integrity is not compromised.
• Critical signals are supported by analysis, modeling, or
technical rationale justifying why they are expected to work.
• Identified critical signals receive special layout attention
assuring their proper functioning
• Signal Integrity analysis, test results, and scope pictures
should be available at the final design review
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Definition of Critical Signals
A line is electrically long when:
Length, L (inches) > 2 X Rise Time, RT
(nsec)
(For a PCB built in FR4 with a di-electric
constant of about 4 and speed of light is
approx 6 inches/sec)
When RT = 1 ns, L = 2 inches
When RT = 8 ns, L = 16 inches
So as edge rates get faster with newer device
technologies, it is becoming more important
to consider transmission line effects,
termination techniques, and matched
impedance in order to ensure signal integrity
performance in the PWB design.
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Definition of Critical Signals
• Characteristics of Critical Signals:
– Edges or levels whose functions would not work should they
receive noise, a double clock, or a glitch.
• Clocks, FIFO Read / Write, Reset, Output Enable
• Analog control and / or monitor lines
– Would stress parts should they over / under shoot
– Rise times faster than the round trip propagation time
– Source or Victims in a noise “Source” “Coupling” “Victim”
analysis
– Need to be stable in time to meet setup, hold, or sampling times
– Cascading consequence with electrical failure or unintended output
glitches
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Definition of Critical Signals (cont.)
• Special attention for critical signals
– Hand routing, short lengths or provisions for
termination resistors
– Isolation from other signals by shields and / or
distance
– Some may not be edge sensitive but they need
to be looked at to make sure that they do not
over / under shoot and cause stress or that they
are stable in time to meet setup and hold times
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Agenda – Common Signal
Integrity Considerations
•
•
•
•
•
Undershoot / overshoot
Ringing
Crosstalk
Timing budgets, skew, setup / hold
Mitigating Signal Integrity Issues: termination,
stack-up, proper routing constraints
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Common Signal Integrity Considerations
• Undershoot / Overshoot
– Reflections may cause voltages to go below or above
the normal voltage range.
– Reflections occur when the propagating signal arrives
at the far end and travels back to the source. This signal
can reflect a second time off the source impedance as it
travels back to the head end
– The undershoot/overshoot may cause damage to the ICs
by damaging input protection circuitry.
– In some situations reflections are required for circuit
operation – i.e.., PCI bus signals, which use reflected
wave signaling.
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Common Signal Integrity
Considerations (cont.)
• Ringing
– Reflections can also cause ringing effects on a signal
trace.
– Ringing can distort the appearance of signals, causing
signal transitions to be smaller or larger at the receiver.
– Can also cause damage to ICs.
– Ringback problems can also cause incorrect logic
switching if the voltage falls between the threshold
voltage range.
– Proper termination can solve overshoot / undershoot,
ringing problems.
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Common Signal Integrity
Considerations (cont.)
• Crosstalk
– Signals on adjacent lines may couple to a given signal
and induce crosstalk.
• Mutual inductance: A magnetic field causes induced
current from the driven wire to appear on the quiet wire.
This mutual inductance causes positive waves to appear
near the transmitter end of the quiet line (near end
inductance) and negative waves at the receiver end of the
transmission line (far end crosstalk).
• Mutual capacitance: The coupling of two electric fields
when current is injected in the quiet line proportional to
the rate of change of voltage in the driver. This mutual
capacitance causes positive waves near both ends of the
transmission line.
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Common Signal Integrity
Considerations (cont.)
• Crosstalk (cont.)
– Crosstalk can add up if traces run parallel of each other
over longer lengths on the PWB.
– Crosstalk can also be induced if the trace spacing is
reduced.
– High density PWBs yield more crosstalk.
– Crosstalk can be mitigated by laying out circuit traces
appropriately – taking consideration of
vertical/horizontal routing, trace width and spacing.
– Need to consider capacitively coupled and inductively
coupled crosstalk components
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Common Signal Integrity
Considerations (cont.)
• Timing
– Setup / hold violations can cause incorrect logic
operation, glitches, metastability
– Logic operating from different oscillators cause
asynchronous interfaces and metastability issues
– Skew of Clock and Data over temperature and / or life
can result in marginal set up / hold times
– Increased skew in the clock distribution system can
reduce design margin
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Mitigating Signal Integrity Issues
•
•
•
•
Selecting termination values
Controlling characteristic impedance
Defining the board stack-up
Constraining the routing
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Selecting Termination Values
• Proper termination technique reduces reflections which
mitigates overshoot, undershoot, ringing problems
• Termination selection must be appropriate for the application,
source / driver topology
• Two common termination topologies:
– Source termination
– End termination
• Four common termination schemes:
– Series termination
– Parallel termination
– Thevenin termination
– AC termination
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Selecting Termination Values (cont.)
• Series Termination
– Simplest termination scheme
– Placed near the source/driver
– Rs is chosen such that the
driver output impedance, Zo +
Rs will match the trace
impedance, Zt
• Parallel Termination
– Placed near receiver.
– Terminate to either Vcc or
Gnd.
– Not good option if need to
terminate many traces, because
of continuous DC current flow
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Selecting Termination Values (cont.)
• Thevenin Termination
– Similar to parallel, but with two
resistors one to Vcc and one to
Gnd.
– Provides pullup-pulldown
function as well as termination.
• AC Termination
– Adds a capacitor in series with
the resister near the destination.
– Capacitor blocks DC current, so
no steady state current as with
parallel.
– However capacitor might effect
the rise/fall times of the signal
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Clock Distribution
● Special care must be taken to ensure proper clock distribution
● Stubs, or excessive loading and route length can cause monotonic
glitches
● The use of a clock buffer should be used to provide clean, point to
point routing from the clock source to each destination in the clock
distribution tree
● Proper termination selection will ensure quiet clock signals
● Other design rules include routing clocks on a “quiet” layer (in
between power planes), minimizing the number of layer switches to
minimize the effects of via discontinuity
● Matched length clock routing to devices ensures that skew will not
decrease timing margins
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Controlling Characteristic Impedance
•
Layer Stack up
– Defines the PWB layer composition
– Stack up defines trace impedance
– Keeping power and ground planes
together maximizes their capacitive
coupling and reduces power supply
noise
– Extra ground planes can be used to
isolate routing layers and reduce
crosstalk
– Controlled Impedance – provides a
deterministic method of matching
signal termination. It is possible to
specify controlled impedance using
the appropriate trace width and
distance from ground. This also
reduces variation in board behavior
with each hardware build
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Agenda – Common Power Integrity
Issues
•
•
•
•
Power / Ground plane noise
Effective plane design
Decoupling, package parasitics
Power distribution system input impedance
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Common Power Integrity Issues
• Power Plane Noise
– Noise comes from current transients caused by rapid
switching.
– Voltage transients cause logic problems as well as EMI
problems.
• Ground Bounce
– Inductance in the leads of device packages cause ground
bounce.
– Ground bounce causes glitches in the logic inputs whenever
the device outputs switch between states.
– Proper bypassing techniques can be followed to mitigate
ground bounce problems.
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Elements in the Power
Distribution System
• Low impedance power planes
• Decoupling capacitors
• Package inductance
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Power Plane Design
● Need to provide low impedance return current path
● Provide solid reference planes parallel to the routed signals
● Consider return current amplitude when determining power plane
thickness (.5, 1, 2 Oz Cu)
● Pair up power and ground layers to provide additional “free”
capacitance, reducing power supply noise
● Use extra ground planes instead of power planes to isolate sets of
routing layers. Use several vias to connect multiple ground layers.
● Minimize plane splits. Split planes create return path discontinuity
● This causes additional crosstalk problems
● When signals travel over the split, this causes additional forward and
reverse crosstalk
● Remember: vias can also create the same effect of a split plane because
the reference plane may change
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Decoupling Considerations
• Bypassing
– Necessary to reduce the effects of ground bounce.
– Bypass caps provide something like a regulated Power / Gnd at
the device package for a short time until the inductance of the
plane can be overcome.
– Transient currents do not have to flow to and from the power
supply then the logic device changes states, they flow to and from
the caps.
– Follow IC manufacturer’s guideline for appropriate bypass
capacitance. Use short wide traces to route capacitor to power /
gnd pins on the IC, place capacitor near component
– Parallel power and ground planes provide another level of bypass
capacitance. This power to ground plane capacitance has zero
lead inductance, no ESR and helps reduce power / ground noise
at high frequencies.
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Decoupling Considerations (cont.)
• Bypassing (cont.)
– Select capacitors with low ESR and ESL
– Consider the resonant frequency of the capacitor
– Consider the capacitors effective decoupling radius:
capacitors used for high frequency switching have a smaller
effective radius then capacitors used for low frequency
switching
– For high frequency noise, place capacitors near the
component being bypassed, ideally next to the power ground
pins with dedicated vias for each capacitor
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IC Package Effects
• RTSX-S package has poor
distribution of power/supply pins
around the package
• In the diagram shown (CQ256):
– GND: GREY, QTY 19
– Core Supply: Red, QTY 9
– IO Supply: Magenta, QTY
12
– User IO: Green, QTY 201
• Inadequate power and ground
pins, distributed unevenly around
the package. Difficult to define
design pin-out without violating
SSO constraints
• This effects the IO current return
paths and decoupling
effectiveness
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IC Package Effects (cont.)
• RTAXS package has superior
distribution of power/supply pins
around the package
• In the diagram shown (CQ352):
– GND: GREY, QTY 56
– Core Supply: Red, QTY 44
– IO Supply: Magenta, QTY 29
– User IO: Green, QTY 179
• Symmetrically distributed power and
ground pins around the package,
proportional to available IO pins. Far
easier to define design pin-out
without violating SSO constraints
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Agenda – Simulation Techniques
• Simulation tool benefits, capabilities
• Types of analysis techniques
• Simulation models: SPICE vs. IBIS
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Guaranteeing the Design: Signal
Integrity Analysis
• Signal integrity analysis is about avoiding problems as opposed
to fixing them.
• SI analysis addresses:
– Timing:
• Avoid functional integrity issues
• Improve timing margins, resolve clock skew issues
– Signal Quality
• Provide proper routing, minimizing reflections,
impedance mismatch
• Avoid using incorrect termination strategy and
termination values
• Avoid false triggering and functional instability caused
by non-monotonic signals
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Guaranteeing the Design: Signal
Integrity Analysis (cont.)
• SI analysis addresses: (cont.)
– Signal quality (cont.)
• Identify constraints (min / max length, impedance, no. of
vias, Er, etc) necessary dielectric material and best trace
length and width geometry.
• Avoid crosstalk issues and improve noise margins
• Avoid unsuitable layout topologies: daisy chain, star, farend cluster
– Power and Ground Distribution
• Power Distribution Architecture including Decoupling
Capacitor placement and sizing
• Define SSO mitigation strategies
• Reduce the level of EMI emission and likelihood of an
EMC failure
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Signal Integrity Simulation Methods
• Paper, back of an envelope, best practice
– Suitable for simple, slow rise time, slow bandwidth,
robust and forgiving designs
• Excel, Power Point, Word
– Summarizing set up hold, static timing
• Spice
– Model circuit at transistor level, does not automatically
take into account PCB parameters
– Mostly used for Analog circuits
– Can model digital devices
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Signal Integrity Simulation Methods (cont.)
• Detailed Board / System Simulations Integrated with PCB
Tools
– Tools import PCB layout and can simulate IO activity
as well as power plane responses
– Appropriate for high speed, dense and complex systems
– Interconnectix Syntheis, Hyperlynx etc
• Detailed PCB layout
• IBIS + Spice
– Speed2000
• Detailed power plane and IC power Quality
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Introduction to Modeling: SPICE
• SPICE simulations model a circuit at transistor level, thus SPICE
models contain detailed information about the circuit and process
parameters which is regarded as proprietary and IC vendors are
reluctant to provide..
• Not all SPICE simulators are fully compatible.
• Although SPICE simulation accuracy is typically very good, a
significant limitation with this type of modeling is simulation
speed.
• SPICE has various simulator options that control accuracy,
convergence and the algorithm type, and any options that are not
consistent might give rise to poor correlation in simulation
results across different simulators.
IBIS is an alternative to SPICE simulation
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Introduction to IBIS Models
• IBIS: Input/Output Buffer Information Specification
from the Electronics Industry Alliance
• IBIS behavioral data is taken from actual devices.
• IBIS models tend to simulate much faster than SPICE
models.
• IBIS Modeling provides a simple table-based buffer
model for semiconductor devices.
• IBIS models can be used to characterize I/V output curves,
rising/falling transition waveforms, and package parasitic
information of the device.
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Introduction to IBIS Models (cont.)
• IBIS models are intended to provide nonproprietary
information about I/O buffers and are more easily available
from different IC vendors
• Non-convergence is eliminated in IBIS simulation.
• Virtually all EDA vendors presently support IBIS models,
and ease of use of these IBIS simulators is generally very
good.
• IBIS models for most devices are freely available over the
Internet making it easy to simulate several different
manufacturers’ devices on the same board.
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Elements of an IBIS Model
[2]
[3]
[4]
[5]
[1]
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Elements of an IBIS Model (cont.)
Element 1: Pull-down
• Describes the I/V characteristics
during pull-down.
• Data for minimum and maximum
current for given voltages.
• Data is taken for -Vcc to 2Vcc as
that allows a behavioral model for
signal reflections caused by
improper termination and
overshoot and undershoot
situations when the protection
diodes are forward biased.
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Element [1]
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Elements of an IBIS Model (cont.)
Element 2: Pull-up
• Describes the pull-up state of the buffer
when the output drives high.
• Data is entered using the formula Vtable
=
Vcc – Voutput
• The minimum and maximum values are
determined by the minimum and
maximum operating temperatures,
supply voltages and process variations.
• Combining the highest current values
with the fastest ramp time and
minimum package characteristics, a fast
model can be derived. A slow model
can be derived by combining the lowest
current with the slowest ramp time and
maximum package characteristics.
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Elements of an IBIS Model (cont.)
Element 3: GND and Power Clamps
• Describes the ground and power clamp
diodes.
• The GND clamp curve is derived from
the ground relative data gathered while
the buffer is in the high-impedance
state and illustrates the region where
the ground clamp diode is active. The
range is from -VCC to VCC.
• The power clamp curve is derived
from the VCC relative data gathered
while the buffer is in a high impedance
state and shows the region where the
power clamp diode is active. This
measurement ranges from VCC to
2VCC.
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Elements of an IBIS Model (cont.)
Element 4: Ramp
• Describes the ramp time for the
pull-up and pull-down devices.
Ensures proper AC operation
of the model.
• The min and max columns
represent the minimum and
maximum slew rates for the
buffers.
• The values represent the
intrinsic values of the
transistors with all package
parasitics and external loads
removed.
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Elements of an IBIS Model (cont.)
Element 5: Package
• Adds the component and
package parasitics.
• C_comp is the capacitance
of the die itself, excluding
the package capacitance.
• Package characteristic
resistance, inductance and
capacitance are added by
R_pkg, L_pkg, and
C_pkg, respectively.
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Creating the IBIS File
• A standard IBIS model file consists of three
sections:
• Header Info–this section contains basic information
about the IBIS file and what data it provides.
• Component, Package, and Pin Info –this section
contains all information regarding the targeted device
package, pin lists, pin operating conditions, and pinto-buffer mapping.
• V-I Behavioral Model–this section contains all data to
recreate I-V curves as well as V-t transition
waveforms, which describe the switching properties
of the particular buffer.
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Example of an IBIS File
Header
Component
Model I-V Data
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Verify all Models!
|***********************************************************************
| RTSX-S IBIS Model (RT54SX32S and RT54SX72S)
|***********************************************************************
[IBIS ver]
3.2
[File name]
rtsxs.ibs
[File Rev]
1.1
[Date]
March 1, 2004
[Disclaimer] All V/I data was verified for accuracy against bench measurements. The measurements were done
on typical production parts. 3.3V PCI model has not been verified against silicon measurements.
Please check Actel IBIS page for updates at http://www.actel.com/
|******************************************************************************
| IBIS file 6325q83f.ibs created by Jason Lew
|******************************************************************************
[IBIS ver] 2.1
[File name] 6325q83f.ibs
[File Rev] 2.x
[Date]
April 9, 2003
[Source]
From Lab mesurement at Quicklogic.
[Disclaimer] This information is for modeling purposes only, and is not guaranteed.
Be aware of what you are using!
Make certain that models come from trusted sources and are verified
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Simulation Tool Capabilities
● Simulation tools incorporate actual board information, traces, routing,
construction
● Provides an environment for single card or multi card system level
simulation
● Post and Pre route simulation possible: pre route simulation drives
generation of routing constraints, placement considerations and
component selection. Post route simulation validates expected design
performance
● Capability to perform corner case simulations, batch simulations,
sweeps across frequency, voltage, temperature conditions
● What-if exploration: easy to vary design parameters, part types, routing
options
● Full board simulation possible – summary reports can pinpoint
possible problem areas anytime during the layout phase
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Simulation Tool Setup
•
•
Import CAD data into Simulation tool (translation
is seamless if using the simulator tool supported
Layout tool). This incorporates trace routing, via,
power plane information into simulation.
Set up simulation environment with different
parameters (as shown below).
Link models
to devices
Generate Stimulus
Define Board Construction
Specify Noise Rules
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Multiboard Environment Setup
● Multi board simulation also
possible
● This environment incorporates:
 Individual plug-in card
simulation models
 Backplane simulation model
 Pin Interconnection RLC
matrix
 Device models
 Noise rules and simulation
stimulus
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Multiboard Environment Setup
● Define System Connectivity
● Plug-in cards can be included or
excluded from the simulation to
create different loading
conditions
● Specify connector pin
matrix. Connection is made
by pin number or net name
● Import connector model to
incorporate pin to pin
contact parasitics
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Agenda – Simulation Examples
•
•
•
•
•
•
•
•
IO selection
Termination selection: point to point, multi drop bus
PCI Backplane design
Corner cases
Timing analysis
Crosstalk mitigation
Characteristic impedance verification
Input impedance plots with decoupling capacitor
effectiveness
• Simultaneous Switching Outputs (SSO) effects
• Transient analysis
• Batch simulations
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FPGA IO Selection Actel RTSX-S
• SX-S IO driver can be either
high slew or low slew, however,
low slew only effects the falling
edge, rising edge rate is not any
slower
• No selectable output drive
options, only one drive strength
available
• Without termination signals are
never seen to remain within the
500mV maximum undershoot
requirement, making terminating
every output necessary even if
design uses slow slew output
driver
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FPGA IO Selection – Actel RTAX
•
•
•
•
•
AX IO driver can be either high slew or
low slew, with slow slew effecting both
edges of the signal
4 output drive options available: 8, 12,
16, 24 mA
The AX slow slew option eliminates
undershoot problems even without
termination: recommended option where
design timing can be met with slow slew
driver
Designers can get some advantage using
a lower drive output, with the high slew
option, though may not be enough to
completely eliminate the need for
termination
Termination may still be required with
high slew drive
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Terminating a Multi-Drop Data Bus
• Data bus with 4 bi-directional loads simulated
• Different routing topologies compared – star,
min-span
• Different termination schemes compared –
source series, destination RC, terminating at
one point or multiple points
• Worst case drivers used – Actel RTSX-S with
fast slew, high output drive
• Star topology seen to have marginal
performance improvement over min-span, but
not sufficient to replace need for termination,
also takes up additional routing resources
• Source series termination at each driver seen
to have best performance
• Similar finding to single source / destination
case
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Simulating a PCI Backplane
• 8 Slot PCI bus with 6 target cards simulated
(2 slots assumed to have no load)
• 2-6 load cases simulated
• PCI CLK speed 33 MHz, with effective data
bus switching rate 16.5MHz
• Various termination option considered:
– Original PCI 10 Ohm stub terminations
– PCI 10 Ohm, with external backplane
diode termination
– PCI stub termination of 25 Ohm with no
external diode
• External diode seen to eliminate undershoot, even with the minimum of 2
loads, however that necessitates additional components on the backplane
• 25 Ohm termination at the target cards (keeping SBC termination at 10
Ohms) reduces undershoot, allows 33 MHz operation when 6 loads are
used in the system and provides best results
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Simulating Corner Cases
Driver
Receiver
Undershoot
w/ Diode
Undershoot
w/o Diode
Slot 8
Slot 5
573.3 mV
677.1 mV
Slot 8
Slot 4
528 mV
702 mV
Slot 8
Slot 3
523.6 mV
681.7 mV
Slot 8
Slot 2
578.1 mV
697 mV
Slot 8
Slot 1
649.4 mV
699.9 mV
● Various loading cases were simulated
● Worse case as well as the typical
values were recorded in a summary
report
Worse Case value
seen on AD18
Typical value
seen on AD23
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Undershoot
w/ Diode
Undershoot
w/o Diode
Driver
Receiver
Slot 8
Slot 1
735.7 mV
763.4 mV
Slot 5
Slot 8
229.2 mV
604.1 mV
Slot 4
Slot 8
393.8 mV
458.3 mV
Slot 3
Slot 8
413.4 mV
634.8 mV
Slot 2
Slot 8
442.6 mV
662.6 mV
Slot 1
Slot 8
407.2 mV
637.4 mV
Implementation
Timing Analysis
● Timing analysis is another area where Multiboard simulation can
provide valuable information
● Rise and Fall time can be determined at destination devices
● Skew between a data bus bits can be measured
● System net delay reports provide best and worse case timing
analysis to determine system timing budgets and margins
Signal Skew
Rise/Fall Time
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Implementation
Mitigating Crosstalk
● Crosstalk reports provide summary information on the victim
net crosstalk value and list of aggressors
● Detailed reports can be generated to evaluate the contribution
of each aggressor signal
● Simulation evaluates all possible driver/receiver combinations
to provide most thorough analysis
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Implementation
Verifying Characteristic Impedance
● It is possible to measure the characteristic impedance
of a signal trace.
● Using IS, importing the board construction, material
properties, and trace width information the actual value
of impedance could be reported for both single ended
and differential traces.
● The expected versus observed was than compared and
changes were made to meet the desired impedance.
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Implementation
Input Impedance – Actel RTSX-S
• Simulations performed to plot input
impedance curve across range of
frequencies with and without decoupling
capacitors
• Assuming .5A current draw and 10%
ripple on supply, target impedance:
– 2.5V * 10/100/.5 = . 5 Ω
– 3.3 * 10/100/.5 = .66 Ω
• Assuming 1.7 ns rise/fall time, signal
bandwidth = .35/Trise = 205 MHz
• SX-S poor package characteristics make
it difficult to meet low impedance power
delivery even with decoupling capacitors
• Careful study must be done to select
capacitors with lowest ESR and ESL at
required frequency
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Implementation
Input Impedance: Actel RTAX
• RTAXS package has superior distribution of
power/supply pins around the package
• Simulations performed to plot input
impedance curve across range of
frequencies with and without decoupling
capacitors for both IO and core voltage
• Assuming .5A current draw and 10% ripple
on supply, target impedance:
– 1.5V * 10/100/.5 = .3 Ω
– 3.3 * 10/100/.5 = .66 Ω
• Assuming 1.7 ns rise/fall time, signal
bandwidth = .35/Trise = 205 MHz
• AX impedance response is much better, and
given careful part selection and routing, it is
possible to meet target impedance
requirements
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Implementation
Choosing the Right Capacitor
● Simulation used to determine
the impedance of FPGA core
voltage delivery path over a
range of frequencies
● Simulation helps find optimum
bypass capacitor placement
and values
● Supply regulator located at
U27
● Impedance simulated at supply
input of U31
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Implementation
Choosing the Right Capacitor
Zin simulated in 3 cases:
● Case 1 (red): With no on board
decoupling capacitors, low frequency
resonance seen
● Case 2 (purple): With decoupling
capacitors, low frequency resonance
much reduced, 1st impedance spike seen
at 800 MHz
● Case 3 (blue): By adding 8 capacitors
with low ESR at 800 MHz, impedance at
that frequency further reduced
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Implementation
Simultaneous Switching Outputs
(SSO) – Actel RTSX-S
•
•
•
•
Simulations performed to plot IO
voltage during a 32-bit bus
switching cycle.
Simulations show that worse case
bus switching could push voltage
outside of 10% tolerance range
This agrees to assessment based on
input impedance analysis
Though real-world is typically
somewhat better than simulation
predicts, few things to consider:
– Difficult to take high fidelity
measurements right on the
Actel supply pin
– Even at room temp, best case
measurement shows voltages
remaining barely within spec
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Implementation
Simultaneous Switching Outputs –
Actel RTAX
• Simulations performed to plot
IO voltage during a 32-bit bus
switching from all zeros to all
Fs.
• Worse case bus switching still
maintains voltages within 10%
tolerance range
• If real-world proves to be
better than simulation (similar
to SX-S package), that will
increase design margin
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Implementation
Backplane Decoupling
• Backplane decoupling
simulated to see if bulk
capacitors are sufficient to
meet low frequency ( at <100
MHz) impedance
requirements
• Assuming 10% ripple on each
supply, target impedance:
– 2.5V * 10/100/1 = .25 Ω
(1A current draw)
– 3.3 * 10/100/3 = .11 Ω
(3A current draw)
– 5 * 10/100/1 = .5 Ω (1A
current draw)
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Implementation
Backplane Transient Simulations
• Backplane simulated to analyze
transient noise on voltage supply
due to current step response.
• Voltage requirement is to remain
within 10% of nominal, during
transient switching event
• Worse case current profiles were
estimated and simulations were
run with each card in the slot
drawing worse case power at the
same time
• Performance noted with and
without capacitors on the
Backplane
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Implementation
Reporting Errors
● Simulation can be used to generate summary and detailed reports of SI issues
● Crosstalk violation report
● Victim and aggressor net details
● Board timing report
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Implementation
Agenda – Comparison Examples
•
•
•
•
•
Xilinx devices
Actel Devices
Clock driver
PCI Backplane termination
Fairchild GTLP Transceiver
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Implementation
How Do the Simulations Hold Up?
• Simulation is only useful when close correlation exists to
the real world
• Designers should take representative measurements to
validate simulation methodology, setup and assumptions
• Compile metrics to act as the basis for interpolating future
results
• Understand the differences between the simulation
environment and real world operating conditions and
incorporate into the analysis
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Implementation
Xilinx Output Comparison
● Signal measured
at receiver
● Simulation at the
same point
● Rise/fall time,
high/low voltage
and wave shape
agree closely in
both simulation
and lab measured
results
Actual Waveforms
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Simulated Waveforms
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Implementation
Clock Driver Output Comparison
● Signal measured at receiver, driver output and
termination resistor pad
● The actual and simulated waveform at all 3 points
agree closely
● Delay between driver output and destination input
agrees
● Wave shape, voltage values agree
● Rise time at destination agree
Actual Waveform
The 3 waveforms show signal measured at:
● Driver output pin (pad 1 of termination
resistor)
● Pad 2 of termination resistor
● Input at destination device pin
Simulated Waveform
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Implementation
SX-S Output Comparison
• Measurement made on Development
Unit which had 33 Ohm termination
resistors
• Fall Time Measurement:
– Simulated: 1.1 ns
– Lab: 1.6 ns
• Undershoot Measurement:
– Simulated: ~600 mV
– Lab: ~500 mV
• Simulated rise and fall times using
Actel models are typically somewhat
faster compared to real-world
measurements, however, the
differential is small enough that
simulation gives a very good
estimation of worse case behavior
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Implementation
AX Output Comparison
● Voltage high/low value agree fairly closely ● Rise time in lab 2.07 ns while in simulation .9 ns
● Simulation shows more ringing then actual ● Fall time in lab 1.485 ns while in simulation .7 ns
Actual Waveforms
2005 MAPLD
Simulated Waveforms
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Implementation
AX Output Comparison (cont.)
● Simulate 3 termination cases: 0 Ohm, 45 Ohm, 56 Ohm
● Simulation shows:
 ~.9V undershoot with 0 Ohm
 ~.58V undershoot with 45 Ohm
 ~.38V undershoot with 56 Ohms
● Measurement shows:
 ~1.1V undershoot with 0 Ohm
 ~.48V undershoot with 45 Ohm
 ~.260 undershoot with 56 Ohm
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Implementation
PCI Data Bus Comparison
• Lab measurement shows close correlation to the
simulated results
• In populated chassis, measurement cannot be
taken at Actel device pin, so for comparisons
simulated waveform and lab measurement taken
at J1 connector pin
• Top right waveform: Lab measurement of signal
with 10 Ohm stub resistor only. Top left
waveform is the simulated result of same signal –
both agree within 100 mV
– Simulated: .81V undershoot
– Measured: .70V undershoot
• Middle right waveform: Lab measurement of
signal with 10 Ohm stub and diode on backplane.
Middle left is the simulated result - again both
agree within 100 mV
– Simulated: .58V undershoot
– Measured: .56V undershoot
• Bottom right waveform: Lab measurement of
signal with 25 Ohm stub and no diode on
backplane. Bottom left is the simulated result again both agree within 100 mV
– Simulated: .21V undershoot
– Measured: .22V undershoot
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Implementation
GTLP Driver Output Comparison
• GTLP Driver output compared with and without 45 Ohm termination
• Correlation between the actual and simulated waveforms is again very high
Simulated Waveforms
Actual Waveforms
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Implementation
Agenda – PCB Design Methodology
•
•
•
•
Generate Requirements
Develop a PCB Flow
Develop routing rules
Development design checklists
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Implementation
Putting it all Together: Generating
PWB Design Requirements
• PWB Design must meet electrical performance over worst
case temperature and voltage
• Define the projects requirement for design margin: a
minimum of 10%, 20%
• Critical signals must be analyzed to detect potential
undershoot, overshoot, ringing, crosstalk problems
• Simulation or analysis results should be compiled and made
available during the board sign off design review
• Guarantee performance by design, not test
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Implementation
Generating a PWB Design Flow
Schematic
Capture
Generate
Netlist
Preliminary
Placement
Pre-Route
Simulation
Placement
Guidelines,
Stack-up
Routing
Rules
Route
PWB
Noise Rules,
Models,
Stimulus
Post-Route
Simulation
Analyze
Results
Iterative
Simulation
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Implementation
Release
PWB
Generating Routing Constraints
● Categorize signals into net classes: critical, non-critical, fast/slow
switching, clocks, control signals, busses, power/ground, digital,
analog
● Associate a design rule with each net class
● Analyze each interface appropriately to determine best routing
topology, termination technique and other constraints
● Work with the PCB vendor to define a stack-up that meets impedance
requirements and is manufacturable
● “Plan” the PCB design: which signals should be routed on which
layers, considering return currents, crosstalk mitigation, signal density
● Interact with the CAD designer
● Write it all down, be methodical, leave nothing to “chance”,
understand all design parameters and how they effect performance
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Implementation
Generating a PWB Design Checklist
• Develop checklists for each stage of the design that meets project standards
• Ensures each engineer will follow a consistent design methodology and design
will meet performance standard with predictable and repeatable results
Y/N
Y/N
•
•
•
•
•
•
•
•
Has the loading of each output signal been
checked and compared with specification of the
IC supplier? This would include maximum
output drive current and capacitance loading?
Has the module’s power up sequence been
analyzed with respect to an IC power
requirement? Has possibility of input latch up
been investigated?
Have all floating input signals been pulled up or
down with resistors? Have you taken into
account that FPGA inputs might be floated on
module power up or FPGA configuration?
Has crosstalk been considered with all possible
steps taken to keep traces spaced out from each
other?
Have all ICs been properly bypassed according to
the manufacturer’s recommendation?
Has all bypassing been checked? Bypassing done
per vendors recommendations, no thin traces,
cap placed closely to IC pin
Has all clock routing been checked? Proper
termination, routed on the right layer, right width
(for controlled impedance), no signals running
parallel closely
•
•
•
•
•
•
Are termination components in the right location –
series near source, end near destination, routed pin 1 st
termination last.
Have all input and output voltages of devices on the
module been checked for being driving by the correct
type of logic. I.e. TTL, CMOS, LVDS?
For FPGAs, has effort been made to eliminate ground
bounce from simultaneous switching outputs by
assigning the proper pinouts?
Have critical setup and hold timing requirements been
identified and analyzed?
Have all of the busses been pulled up to prevent
oscillation or has the use of bus-hold logic been
implemented?
Has the power routing/distribution been checked?
Have area fills been considered carefully verifying that
the fills will not modify the stackup and effect the
impedance?
Have all the interconnects been checked looking
carefully at: routing – going from right source to
destination, lengths are not unnecessarily long, doing
loops, No T or Y junctions, all multiple destination
traces daisy chained to minimize stub length, on the
right layers/widths for controlled impedance
Example Checklist
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Implementation
References
● Klabs.org
● Mike Bay, Solar Dynamics
Observatory System Engineer,
GSFC
● High Speed Digital Design by
Howard W. Johnson and Martin
Graham
● http://www.eigroup.org/ibis/
● http://www.actel.com/techdocs/
models/ibis.html
● http:// www.mentor.com/icx
● http://www.sigrity.com/support/
techpapers/support_tech_doc.htm
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Implementation