Transcript PRETLabVIEWDSRT2008 - University of California, Berkeley

An Automated Mapping of Timed
Functional Specification to A Precision
Timed Architecture
Shanna-Shaye Forbes*, Hugo A. Andrade**, Hiren D. Patel* and Edward A. Lee*
Presented by
Shanna-Shaye Forbes
[email protected]
*University of California, Berkeley
*National Instruments Corporation
IEEE International Symposium on Distributed
Simulation and Real-Time Applications
October 27, 2008
Vancouver, British Columbia, Canada
Overview
Programming languages generally abstract away the notion of timing at the software level. We overcome
this shortcoming by combining an architecture which has repeatable timing with a model based
programming model with temporal semantics.
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PRET:Precision Timed Machines
• ISA extensions with timing instructions
• Multithreaded architecture with
scratchpad memories and time-triggered
access to main memory
• Simulator accepts programs in C with
additional timing instructions.
Related Work
• JOP(Vienna), SPEAR(Vienna), KEP(Kiel),
REMIC (Auckland)
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LabVIEW
• Actor oriented structured data flow
programming language G
• C software synthesis backend to
automatically generate code
• Has the ability to incorporate legacy C
code into a model based design
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LabVIEW cont.
• Timed loops allow the user to specify the
period and offset at which functions are to
be executed
An Automated Mapping of Timed Functional Specification to A
Precision Timed Architecture, Forbes
IEEE DS-RT, Oct. 27, 2008
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Timed Loop
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Plug-in
• LabVIEW has a plug-in architecture.
• We implemented a plug-in that maps
LabVIEW to the PRET architecture.
• Implements timed loops with the PRET
timing instruction.
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Simple mutual exclusion example
Producer
Observer
Consumer
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Questions?
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Demo
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