Transcript chapter7 Instruction Set Architecture (ISA)

Chapter7:
Instruction Sets:
Characteristics
Functions
Addressing Modes
Formats
What is an Instruction Set?
The complete collection of instructions
that are understood by a CPU
Machine Code
Binary
Usually represented by assembly
codes
What is the Instruction Set Architecture?
It contains instructions to use and
manipulate programmer-accessible
hardware in a computer.
in terms of
place in a
computer
What is the relationship between the
Instruction Set Architecture and
Assembly / Machine language?
An assembly / machine program is made up
of the instructions in the ISA and makes
use of registries in the ISA.
Here’s how it works
Higher level languages (Java, C++, etc…)
are translated into assembly / machine
language by compilers.
When a user calls the program, the
compiled program is loaded into RAM.
The program then executes, line by line,
until the Operating System takes back
control of the computer.
Elements of an Instruction
Operation code (Op code)
 Do this
Source Operand reference
 To this
Result Operand reference
 Put the answer here
Next Instruction Reference
 When you have done that, do this...
Where have all the Operands Gone?
Main memory (or virtual memory or
cache)
CPU register
I/O device
Instruction Cycle State Diagram
Instruction Representation
In machine code each instruction has a
unique bit pattern
For human consumption (well,
programmers anyway) a symbolic
representation is used
 e.g. ADD, SUB, LOAD
Operands can also be represented in this
way
 ADD A,B
Simple Instruction Format
Instruction Types
Data processing
Data storage (main memory)
Data movement (I/O)
Program flow control
Number of Addresses (a)
3 addresses
 Operand 1, Operand 2, Result
 a = b + c;
 May be a forth - next instruction (usually
implicit)
 Not common
 Needs very long words to hold everything
Number of Addresses (b)
2 addresses




One address doubles as operand and result
a=a+b
Reduces length of instruction
Requires some extra work
– Temporary storage to hold some results
Number of Addresses (c)
1 address
 Implicit second address
 Usually a register (accumulator)
 Common on early machines
Number of Addresses (d)
0 (zero) addresses
 All addresses implicit
 Uses a stack
 e.g. push a
push b
add
pop c
 c=a+b
How Many Addresses
More addresses
 More complex (powerful?) instructions
 More registers
– Inter-register operations are quicker
 Fewer instructions per program
Fewer addresses
 Less complex (powerful?) instructions
 More instructions per program
 Faster fetch/execution of instructions
Design Decisions (1)
Operation repertoire
 How many ops?
 What can they do?
 How complex are they?
Data types
Instruction formats
 Length of op code field
 Number of addresses
Design Decisions (2)
Registers
 Number of CPU registers available
 Which operations can be performed on which
registers?
Addressing modes
RISC v CISC
Types of Operand
Addresses
Numbers
 Integer/floating point
Characters
 ASCII etc.
Logical Data
 Bits or flags
x86 Data Types
8 bit Byte
16 bit word
32 bit double word
64 bit quad word
128 bit double quadword
Addressing is by 8 bit unit
Words do not need to align at evennumbered address
Data accessed across 32 bit bus in units
of double word read at addresses divisible
by 4
Little endian
SMID Data Types
 Integer types
— Interpreted as bit field or integer
 Packed byte and packed byte integer
— Bytes packed into 64-bit quadword or 128-bit double
quadword
 Packed word and packed word integer
— 16-bit words packed into 64-bit quadword or 128-bit double
quadword
 Packed doubleword and packed doubleword integer
— 32-bit doublewords packed into 64-bit quadword or 128-bit
double quadword
 Packed quadword and packed qaudword integer
— Two 64-bit quadwords packed into 128-bit double quadword
 Packed single-precision floating-point and packed doubleprecision floating-point
— Four 32-bit floating-point or two 64-bit floating-point values
packed into a 128-bit double quadword
x86 Numeric Data Formats
ARM Data Types
 8 (byte), 16 (halfword), 32 (word) bits
 Halfword and word accesses should be word aligned
 Nonaligned access alternatives
— Default
–
–
–
–
Treated as truncated
Bits[1:0] treated as zero for word
Bit[0] treated as zero for halfword
Load single word instructions rotate right word aligned data transferred by
non word-aligned address one, two or three bytesAlignment checking
— Data abort signal indicates alignment fault for attempting unaligned
access
— Unaligned access
— Processor uses one or more memory accesses to generate transfer of
adjacent bytes transparently to the programmer
 Unsigned integer interpretation supported for all types
 Twos-complement signed integer interpretation supported for all
types
 Majority of implementations do not provide floating-point
hardware
—
—
—
—
Saves power and area
Floating-point arithmetic implemented in software
Optional floating-point coprocessor
Single- and double-precision IEEE 754 floating point data types
ARM Endian Support
E-bit in system control register
Under program control
Types of Operation
Data Transfer
Arithmetic
Logical
Conversion
I/O
System Control
Transfer of Control
Types of Operation: Data Transfer
Specify
—Source
—Destination
—Amount of data
May be different instructions for different
movements
—e.g. IBM 370
Or one instruction and different addresses
—e.g. VAX
Note: VAX was an ISA developed by Digital Equipment Corporation (DEC) in the
mid-1970s. A 32-bit instruction set computer (CISC) ISA, it was designed to
extend or replace DEC's various Programmed Data Processor (PDP) ISAs.
The VAX name was also used by DEC for a family of computer systems
based on this processor architecture.
Types of Operation: Arithmetic
Add, Subtract, Multiply, Divide
Signed Integer
Floating point ?
May include
—Increment (a++)
—Decrement (a--)
—Negate (-a)
Types of Operation:
Shift and Rotate Operations
Types of Operation: Logical
Bitwise operations
 AND, OR, NOT
Types of Operation: Conversion
E.g. Binary to Decimal
Types of Operation: Input / Output
May be specific instructions
May be done using data movement
instructions (memory mapped)
May be done by a separate controller
(DMA)
Types of Operation: Systems Control
Privileged instructions
CPU needs to be in specific state
—Ring 0 on 80386+
—Kernel mode
For operating systems use
Transfer of Control
Branch
—e.g. branch to x if result is zero
Skip
—e.g. increment and skip if zero
—ISZ Register1
—Branch xxxx
—ADD A
Subroutine call
—c.f. interrupt call
Transfer of Control: Branch Instruction
Nested Procedure Calls
Use of Stack
Stack Frame Growth Using Sample
Procedures P and Q
Byte Order (A portion of chips?)
What order do we read numbers that
occupy more than one byte
e.g. (numbers in hex to make it easy to
read)
12345678 can be stored in 4x8bit
locations as follows
Byte Order (example)
Address
184
185
186
186
Value (1)
12
34
56
78
Value(2)
78
56
34
12
i.e. read top down or bottom up?
Byte Order Names
The problem is called Endian
The system on the left has the least
significant byte in the lowest address and
this is called big-endian
The system on the right has the least
significant byte in the highest address and
this is called little-endian
Example of C Data Structure
Alternative View of Memory Map
Standard…What Standard?
Pentium (x86), VAX are little-endian
IBM 370, Motorola 680x0 (Mac), and most
RISC are big-endian
Internet is big-endian
—Makes writing Internet programs on PC more
awkward!
—WinSock provides htoi and itoh (Host to
Internet & Internet to Host) functions to
convert
Addressing Modes
Immediate
Direct
Indirect
Register
Register Indirect
Displacement (Indexed)
Stack
Addressing Modes: Immediate Addressing
Operand is part of instruction
Operand = address field
e.g. ADD 5
—Add 5 to contents of accumulator
—5 is operand
No memory reference to fetch data
Fast
Limited range
Addressing Modes:
Immediate Addressing Diagram
Instruction
Opcode
Operand
Addressing Modes: Direct Addressing
Address field contains address of operand
Effective address (EA) = address field (A)
e.g. ADD A
—Add contents of cell A to accumulator
—Look in memory at address A for operand
Single memory reference to access data
No additional calculations to work out
effective address
Limited address space
Addressing Modes:
Direct Addressing Diagram
Instruction
Opcode
Address A
Memory
Operand
Addressing Modes:
Indirect Addressing (1)
Memory cell pointed to by address field
contains the address of (pointer to) the
operand
EA = (A)
—Look in A, find address (A) and look there for
operand
 e.g. ADD (A)
—Add contents of cell pointed to by contents of
A to accumulator
Addressing Modes:
Indirect Addressing (2)
Large address space
2n where n = word length
May be nested, multilevel, cascaded
—e.g. EA = (((A)))
– Draw the diagram yourself
Multiple memory accesses to find operand
Hence slower
Addressing Modes:
Indirect Addressing Diagram
Instruction
Opcode
Address A
Memory
Pointer to operand
Operand
Addressing Modes:
Register Addressing (1)
Operand is held in register named in
address filed
EA = R
Limited number of registers
Very small address field needed
—Shorter instructions
—Faster instruction fetch
Addressing Modes:
Register Addressing (2)
No memory access
Very fast execution
Very limited address space
Multiple registers helps performance
—Requires good assembly programming or
compiler writing
—N.B. C programming
– register int a;
c.f. Direct addressing
Addressing Modes:
Register Addressing Diagram
Instruction
Opcode
Register Address R
Registers
Operand
Addressing Modes :
Register Indirect Addressing
C.f. indirect addressing
EA = (R)
Operand is in memory cell pointed to by
contents of register R
Large address space (2n)
One fewer memory access than indirect
addressing
Addressing Modes :
Register Indirect Addressing Diagram
Instruction
Opcode
Register Address R
Memory
Registers
Pointer to Operand
Operand
Addressing Modes:
Displacement Addressing
EA = A + (R)
Address field hold two values
—A = base value
—R = register that holds displacement
—or vice versa
Addressing Modes :
Displacement Addressing Diagram
Instruction
Opcode Register R Address A
Memory
Registers
Pointer to Operand
+
Operand
Addressing Modes :
Relative Addressing
A version of displacement addressing
R = Program counter, PC
EA = A + (PC)
i.e. get operand from A cells from current
location pointed to by PC
c.f locality of reference & cache usage
Addressing Modes:
Base-Register Addressing
A holds displacement
R holds pointer to base address
R may be explicit or implicit
e.g. segment registers in 80x86
Addressing Modes:
Indexed Addressing
A = base
R = displacement
EA = A + R
Good for accessing arrays
—EA = A + R
—R++
Addressing Modes:
Combinations
Postindex
 EA = (A) + (R)
Preindex
 EA = (A+(R))
Addressing Modes:
Stack Addressing
Operand is (implicitly) on top of stack
e.g.
—ADD
Pop top two items from stack
and add
Addressing Modes:
x86 Addressing Modes
 Virtual or effective address is offset into segment
— Starting address plus offset gives linear address
— This goes through page translation if paging enabled
 12 addressing modes available
— Immediate
— Register operand
— Displacement
— Base
— Base with displacement
— Scaled index with displacement
— Base with index and displacement
— Base scaled index with displacement
— Relative
Addressing Modes:
x86 Addressing Mode Calculation
ARM Addressing Modes Load/Store
 Only instructions that reference memory
 Indirectly through base register plus offset
 Offset
— Offset added to or subtracted from base register contents to
form the memory address
 Preindex
— Memory address is formed as for offset addressing
— Memory address also written back to base register
— So base register value incremented or decremented by offset
value
 Postindex
— Memory address is base register value
— Offset added or subtracted
Result written back to base register
 Base register acts as index register for preindex and
postindex addressing
 Offset either immediate value in instruction or another
register
 If register scaled register addressing available
— Offset register value scaled by shift operator
— Instruction specifies shift size
ARM Indexing Methods
ARM Data Processing Instruction Addressing
& Branch Instructions
Data Processing
 Register addressing
– Value in register operands may be scaled using a
shift operator
 Or mixture of register and immediate
addressing
Branch
 Immediate
 Instruction contains 24 bit value
 Shifted 2 bits left
– On word boundary
– Effective range +/-32MB from PC.
ARM Load/Store Multiple Addressing
Load/store subset of general-purpose
registers
16-bit instruction field specifies list of
registers
Sequential range of memory addresses
Increment after, increment before,
decrement after, and decrement before
Base register specifies main memory
address
Incrementing or decrementing starts
before or after first memory access
ARM Load/Store Multiple Addressing Diagram
Instruction Formats
Layout of bits in an instruction
Includes op code
Includes (implicit or explicit) operand(s)
Usually more than one instruction format
in an instruction set
Instruction Length
Affected by and affects:





Memory size
Memory organization
Bus structure
CPU complexity
CPU speed
Trade off between powerful instruction
repertoire and saving space
Allocation of Bits
Number of addressing modes
Number of operands
Register versus memory
Number of register sets
Address range
Address granularity
PDP-8 Instruction Format
PDP-10 Instruction Format
PDP-11 Instruction Format
VAX Instruction Examples
x86 Instruction Format
ARM Instruction Formats






S = For data processing instructions, updates condition codes
S = For load/store multiple instructions, execution restricted to supervisor
mode
P, U, W = distinguish between different types of addressing mode
B = Unsigned byte (B==1) or word (B==0) access
L = For load/store instructions, Load (L==1) or Store (L==0)
L = For branch instructions, is return address stored in link register
ARM Immediate Constants Fig 11.11
Thumb Instruction Set
Re-encoded subset of ARM instruction set
Increases performance in 16-bit or less
data bus
Unconditional (4 bits saved)
Always update conditional flags
—Update flag not used (1 bit saved)
Subset of instructions
—2 bit op code, 3 bit type field (1 bit saved)
—Reduced operand specifications (9 bits saved)
Expanding Thumb ADD Instruction to ARM
Equivalent Fig 11.12
Assembler
Machines store and understand binary
instructions
E.g. N= I + J + K initialize I=2, J=3, K=4
Program starts in location 101
Data starting 201
Code:
Load contents of 201 into AC
Add contents of 202 to AC
Add contents of 203 to AC
Store contents of AC to 204
Tedious and error prone
Improvements
Use hexadecimal rather than binary
—Code as series of lines
– Hex address and memory address
—Need to translate automatically using program
Add symbolic names or mnemonics for
instructions
Three fields per line
—Location address
—Three letter op code
—If memory reference: address
Need more complex translation program
Program in:
Binary
Address
Hexadecimal
Contents
Address
Contents
101
0010
0010
101
2201
101
2201
102
0001
0010
102
1202
102
1202
103
0001
0010
103
1203
103
1203
104
0011
0010
104
3204
104
3204
201
0000
0000
201
0002
201
0002
202
0000
0000
202
0003
202
0003
203
0000
0000
203
0004
203
0004
204
0000
0000
204
0000
204
0000
Symbolic Addresses
First field (address) now symbolic
Memory references in third field now
symbolic
Now have assembly language and need
an assembler to translate
Assembler used for some systems
programming
—Compliers
—I/O routines
Symbolic Program
Address
Instruction
101
LDA
201
102
ADD
202
103
ADD
203
104
STA
204
201
DAT
2
202
DAT
3
203
DAT
4
204
DAT
0
Assembler Program
Label
Operation
Operand
FORMUL
LDA
I
ADD
J
ADD
K
STA
N
I
DATA
2
J
DATA
3
K
DATA
4
N
DATA
0
END OF ISA