Transcript Addressing Modes

William Stallings
Computer Organization
and Architecture
6th Edition
Chapter 11
Instruction Sets:
Addressing Modes
and Formats
Addressing Modes p.352
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Immediate
Direct
Indirect
Register
Register Indirect
Displacement (Indexed)
Stack
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Immediate Addressing 즉치주소 p.354
• Operand is part of instruction
• Operand = address field
• e.g. ADD 5
—Add 5 to contents of accumulator
—5 is operand
• No memory reference to fetch data
• Fast
• Limited range
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Immediate Addressing Diagram
Instruction
Opcode
Operand
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Direct Addressing 직접주소 p.355
• Address field contains address of operand
• Effective address (EA) = address field (A)
• e.g. ADD A
—Add contents of cell A to accumulator
—Look in memory at address A for operand
• Single memory reference to access data
• No additional calculations to work out effective
address
• Limited address space
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Direct Addressing Diagram
Instruction
Opcode
Address A
Memory
Operand
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Indirect Addressing (1) 간접주소 p.355
• Memory cell pointed to by address field contains
the address of (pointer to) the operand
• EA = (A)
—Look in A, find address (A) and look there for
operand
• e.g. ADD (A)
—Add contents of cell pointed to by contents of A to
accumulator
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Indirect Addressing (2)
• Large address space
• 2n where n = word length
• May be nested, multilevel, cascaded
—e.g. EA = (((A)))
– Draw the diagram yourself
• Multiple memory accesses to find operand
• Hence slower
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Indirect Addressing Diagram
Instruction
Opcode
Address A
Memory
Pointer to operand
Operand
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Register Addressing (1) p.356
• Operand is held in register named in address
filed
• EA = R
• Limited number of registers
• Very small address field needed
—Shorter instructions
—Faster instruction fetch
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Register Addressing (2)
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No memory access
Very fast execution
Very limited address space
Multiple registers helps performance
—Requires good assembly programming or compiler
writing
—N.B. C programming
– register int a;
• c.f. Direct addressing
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Register Addressing Diagram
Instruction
Opcode
Register Address R
Registers
Operand
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Register Indirect Addressing p.357
• C.f. indirect addressing
• EA = (R)
• Operand is in memory cell pointed to by
contents of register R
• Large address space (2n)
• One fewer memory access than indirect
addressing
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Register Indirect Addressing Diagram
Instruction
Opcode
Register Address R
Memory
Registers
Pointer to Operand
Operand
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Displacement Addressing p.357
• EA = A + (R)
• Address field hold two values
—A = base value
—R = register that holds displacement
—or vice versa
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Displacement Addressing Diagram
Instruction
Opcode Register R Address A
Memory
Registers
Pointer to Operand
+
Operand
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Relative Addressing p.358
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A version of displacement addressing
R = Program counter, PC
EA = A + (PC)
i.e. get operand from A cells from current
location pointed to by PC
• c.f locality of reference & cache usage
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Base-Register Addressing p.358
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A holds displacement
R holds pointer to base address
R may be explicit or implicit
e.g. segment registers in 80x86
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Indexed Addressing p.358
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A = base
R = displacement
EA = A + R
Good for accessing arrays
—EA = A + R
—R++
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Combinations
• Postindex
• EA = (A) + (R)
• Preindex
• EA = (A+(R))
• (Draw the diagrams)
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Stack Addressing
p.360
• Operand is (implicitly) on top of stack
• e.g.
—ADD
Pop top two items from stack
and add
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Pentium Addressing Modes
• Virtual or effective address is offset into segment
— Starting address plus offset gives linear address
— This goes through page translation if paging enabled
• 12 addressing modes available
— Immediate
— Register operand
— Displacement
— Base
— Base with displacement
— Scaled index with displacement
— Base with index and displacement
— Base scaled index with displacement
— Relative
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Pentium Addressing Mode Calculation
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Instruction Formats p.367
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Layout of bits in an instruction
Includes opcode
Includes (implicit or explicit) operand(s)
Usually more than one instruction format in an
instruction set
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Instruction Length p.367
• Affected by and affects:
—Memory size : 기억용량
—Memory organization 기억장치의 구조
—Bus structure : 버스의 구조
—CPU complexity : CPU의 복잡도
—CPU speed : 속도
• Trade off between powerful instruction
repertoire and saving space
—명령어의 종류를 늘리는 것과 공간을 절약하는 것
상사이의 조정
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Allocation of Bits p.368
• Number of addressing modes
—주소지정 방식들의 수
• Number of operands
—오퍼랜드의 수
• Register versus memory
• Number of register sets
—레지스테 세트의 수
• Address range
—주소영역
• Address granularity
—주소의 세분화
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PDP-8 Instruction Format
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PDP-10 Instruction Format
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PDP-11 Instruction Format
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VAX Instruction Examples
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Pentium Instruction Format
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PowerPC Instruction Formats (1)
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PowerPC Instruction Formats (2)
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Foreground Reading
• Stallings chapter 11
• Intel and PowerPC Web sites
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