Transcript TK2123-Lecture14-Instruction Set Architecture Level

TK 2123
Lecture 14: Instruction Set
Architecture Level (Level 2)
Ass. Prof. Dr Masri Ayob
ISA Level
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OS level – ISA level- Microarchitecture level.
Historically, ISA level was developed before any of
the other levels (originally the only level).
Sometimes referred as “the architecture” of a
machine or “assembly language” (incorrect).
Interface between software and hardware.
The ISA level defines the interface between the
compilers and hardware.
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ISA Level
The ISA level is
the interface
between the
compilers and
the hardware.
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ISA Level
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Is defined by how the machine appears to a machine
language programmer.
 No person does machine language
programming.
 Redefined:
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ISA-level code is what a compiler outputs.
The compiler writer has to know:
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Memory model
Registers
Data type
Addressing mode
Instruction set .
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Memory Models
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What order do we read numbers that occupy
more than one byte
e.g. (numbers in hex to make it easy to read)
12345678 can be stored in 4x8bit locations as
follows
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Memory Models (example)
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Address
184
185
186
186
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i.e. read top down or bottom up?
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Value (1)
12
34
56
78
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Value(2)
78
56
34
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Memory Models
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The problem is called Endian
The system on the left has the most
significant byte in the smallest address:
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Big-endian
The system on the right has the least
significant byte in the smallest address:
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Little-endian
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Example of C Data Structure
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Standard…What Standard?
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Pentium (80x86), VAX are little-endian
IBM 370, Motorola 680x0 (Mac), and most
RISC are big-endian
Internet is big-endian.
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What is an Instruction Set?
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The complete collection of instructions that
are understood by a CPU
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Machine Code
Binary
Usually represented by assembly codes
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Elements of an Instruction
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Operation code (Opcode)
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Source Operand reference
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To this..i.e. the data to be operated on
Result Operand reference
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Do this…i.e. the task to be performed
Put the answer here…..
Next Instruction Reference
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When you have done that, do this...
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Where have all the Operands Gone?
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Main memory (or virtual memory or cache)
CPU register
I/O device
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Instruction Cycle State Diagram
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Instruction Representation
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In machine code each instruction has a unique bit
pattern
For human consumption (well, programmers anyway)
a symbolic representation is used
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Operands can also be represented in this way
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e.g. ADD, SUB, LOAD
ADD A,B
Usually there are not enough bits in one byte to store
enough instructions and addresses:
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Instructions stored in more than one byte.
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Simple Instruction Format
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Number of Addresses (a)
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3 addresses
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Operand 1, Operand 2, Result
a = b + c;
May be a forth - next instruction (usually
implicit)
Not common
Needs very long words to hold everything
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Number of Addresses (b)
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2 addresses
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One address doubles as operand and result
a=a+b
Reduces length of instruction
Requires some extra work
 Temporary storage to hold some results
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Number of Addresses (c)
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1 address
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Implicit second address
Usually a register (accumulator)
Common on early machines
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Number of Addresses (d)
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0 (zero) addresses
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All addresses implicit
Uses a stack
e.g. push a
push b
add
pop c
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How Many Addresses
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More addresses
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More complex (powerful?) instructions
More registers
 Inter-register operations are quicker
Fewer instructions per program
Fewer addresses
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Less complex (powerful?) instructions
More instructions per program
Faster fetch/execution of instructions
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Design Decisions (1)
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Operation issues:
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How many ops?
What can they do?
How complex are they?
Data types
Instruction formats
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Length of op code field
Number of addresses
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Design Decisions (2)
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Registers
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Number of CPU registers available
Which operations can be performed on
which registers?
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Addressing modes (later…)
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RISC v CISC
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Addressing Modes
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Instructions can be categorized according to their
method of addressing the hardware registers
and/or memory.
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Implied Addressing
Register Addressing
Immediate Addressing
Direct Addressing
Register Indirect Addressing
Combined Addressing Modes.
The various ways of addressing data in an instruction are
known as addressing mode.
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Implied Addressing
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The addressing mode of certain instructions is
implied by the instruction’s function.
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For example:
 the STC (set carry flag) instruction deals only
with the carry flag
 the DAA (decimal adjust accumulator)
instruction deals with the accumulator.
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Register Addressing
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The accumulator is implied as a second operand.
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For example,
 the instruction CMP E may be interpreted as
'compare the contents of the E register with
the contents of the accumulator.
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Immediate Addressing
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These instructions have data assembled as a part
of the instruction itself.
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For example, the instruction CPI 'C' may be
interpreted as ‘compare the contents of the
accumulator with the letter C.
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Direct Addressing
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These instructions directly specify the memory
address of the operand.
Example:
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JMP 1000H causes a jump to the address 1000H
by replacing the current contents of the PC with
the new value 1000H.
LDA 2000H will load the contents of memory
location 2000H into the accumulator.
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Register Indirect Addressing
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These instructions reference memory via a
register pair.
For example:
MOV M,C
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moves the contents of the C register into the
memory location pointed by the H and L register
pair.
The instruction LDAX B loads the accumulator
with the byte of data specified by the address in
the B and C register pair .
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Combined Addressing Modes
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Some instructions use a combination of
addressing modes.
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A CALL instruction, for example, combines direct
addressing and register indirect addressing.
The direct address in a CALL instruction specifies
the address of the desired subroutine;
the register indirect address is the stack pointer.
The CALL instruction pushes the current
contents of the program counter into the
memory location specified by the stack pointer. .
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Discussion of Addressing Modes
A comparison of addressing modes.
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Timing Effects of Addressing Modes
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Addressing modes affect both:
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the amount of time required for executing an instruction.
the amount of memory required for its storage.
For example, instructions that use implied or register
addressing, execute very quickly since they deal directly
with the processor’s hardware or with data already
present in hardware registers.
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the entire instruction can be fetched with a single memory
access.
The number of memory accesses required is the greatest
factor in determining execution timing.
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Timing Effects of Addressing Modes
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More memory accesses require more execution
time.
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A CALL instruction, for example, requires five
memory accesses: three to access the entire
instruction and two more to push the contents of
the program counter onto the stack.
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Types of Operand
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Addresses
Numbers
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Characters
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Integer/floating point
ASCII etc.
Logical Data
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Bits or flags
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Pentium Data Types
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8 bit Byte
16 bit word
32 bit double word
64 bit quad word
Addressing is by 8 bit unit
A 32 bit double word is read at addresses
divisible by 4
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Types of Instruction Operation
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Data Transfer (data movement)
Arithmetic
Logical
Conversion
I/O
System Control
Program Control
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Data Transfer (Data Movement)
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Specify
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May be different instructions for different
movements
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e.g. IBM 370
Or one instruction and different addresses
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Source
Destination
Amount of data
e.g. VAX
E.g. MOV A,B
Move 8-bit data from register B to accumulator A.
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Data Transfer (Data Movement)
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Data Movement Instructions are the most
frequently used and computer designers provide
a lot of flexibility to these instructions.
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E.g. Intel 8085 provides data transfer between:
 Register-to-register
 Register-to-memory
 Memory-to-register
 Stack operation.
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Arithmetic
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Add, Subtract, Multiply, Divide
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E.g. ADD C
Add the content of register C to the content of
accumulator A.
Signed Integer
Floating point ?
May include
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Increment (a++)
Decrement (a--)
Negate (-a)
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Shift and Rotate Operations
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Logical
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Bitwise operations
AND, OR, NOT
Example:
ANA B A= A AND B
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Conversion
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E.g. Binary to Decimal
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Input/Output
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May be specific instructions
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E.g. IN 12 Read input data from port
location 12
May be done using data movement
instructions (memory mapped)
May be done by a separate controller (DMA)
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Systems Control
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Privileged instructions
CPU needs to be in specific state
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Ring 0 on 80386+
Kernel mode
For operating systems use
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Program Control Instructions
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Branch/Jump
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Skip
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e.g. increment and skip if zero
 ISZ Register1
Branch xxxx
Subroutine call
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e.g. branch to x if result is zero
 JZ
E.g. CALL sum
Return from subroutine
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E.g. RET
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Nested Procedure Calls
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Use of Stack
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The Pentium 4’s
primary
registers.
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The Pentium 4 Instruction Formats
The Pentium 4 instruction formats.
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Example of 8051 Instructions
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More……
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Thank you
Q&A
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