Transcript CISC v RISC

RISC and CISC
RISC versus CISC
The world of microprocessors and CPUs can be divided
into two parts: complex instruction set computers using
CISC processors, and reduced instruction set computers with
RISC processors.
Example:
Intel’s Pentium-class microprocessors – CISC
Sun’s SPARC microprocessors - RISC
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Why RISC?
– First microprocessors used very simple instruction sets.
– As microprocessors became more complex, then more
instructions incorporated. (>300 current CISC).
– Some instructions used frequently, others are very
specialised and used rarely.
– In general, the more instructions there are in an
instruction set, then the longer the propagation delay in
the CPU. (More logic to decode instructions needed).
– ANSWER: to speed up CPU, then reduce instruction
set. (<100 current RISC). But, there is a problem with
this.
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The RISC Tradeoff
– The eliminated instructions generally correspond to
specific statements in higher-level languages.
Eliminating these would force the CPU to use several
instructions instead of one to perform the same function
(if required by the program). This would invariably
require more time.
– Example: AND, OR, XOR, and NOT
• Eliminate OR and XOR instructions because they can be
constructed from AND and NOT instructions (DeMorgan’s
etc. – think what we saw in LC-3).
– SUB
• Can be implemented using addition and 2’s complement
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The RISC CPU - features
• Reduced instruction set size
• Fixed length instructions
• Limited instructions for interaction with memory
for loading and storing data
• Fewer addressing modes
• Instruction pipeline
• Large number of registers
• Hardwired control unit
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Fixed length instructions
In a RISC CPU, every instruction has the
same number of bits. Each instruction is
capable of being executed in a single clock
cycle.
You will have seen this with the LC-3
instructions/architecture.
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Limited memory interaction
instructions
All processors can load and store data to and
from memory, but CISC includes other
capabilities, e.g. ANDing accumulator
contents with memory. RISC first loads
value into register, then performs AND
operation
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Fewer addressing modes
Some addressing modes require several
memory accesses which degrades
performance. RISC CPUs allow only a few
addressing modes that can be processed
quickly
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Instruction pipeline
– One instruction is executed while the next
instruction is being decoded and its operands
are being loaded, while the next instruction is
being fetched. By overlapping these operations
(like assembly pipeline), the CPU executes one
instruction per clock cycle
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Many registers
• Having a large number of registers allows
the CPU to store many operands internally,
rather than in memory. This reduces access
time significantly
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Hardwired Control Unit
• A CISC processor uses microprogramming
rather than a hard-wired CU
• Microencoding of machine instructions is
easy, and allows for backwards compatibility
• But hardwired logic has a lower propagation
delay, hence RISC CUs run faster, but are not
as easy to modify
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So, which is better?
For RISC:
1. Control units are less complex, and easier
to design, so they can run at higher clock
frequencies than CISC. They are also
smaller, allowing more room for extra
registers and other components. Simpler
design makes them easier to use in parallel
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Which is better?
For RISC:
2. Fewer instructions means compilers are
less complex than for CISC processors
(though will probably need many more
machine code instructions); ideal for HLL
programming (but CISC is better for
Assembly Language programming)
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Which is better?
For CISC:
1. Maybe more complex to design, but latest
chips are often built on previous ones (e.g.
Intel Pentium), so development costs
might not be higher, and may actually be
lower. Also means technology is tried and
tested
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Which is better?
For CISC:
2. Backwards compatibility – can run the
same software as previous versions of the
processor
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Which is better?
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The jury is still out
Some believe RISC will out-compete CISC
Others believe they will co-exist
Others foresee a hybrid CPU
But there are lots of heated debates going
on!
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Intermingling
• Intermingling of RISC and CISC concepts
is already underway, with CISC processors
incorporating pipelining
• CISC processors are incorporating more
registers too, as improved technology
allows
• The PowerPC (now defunct) was an
example of a hybrid
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The LC-3 is RISC
• How do you know this from your knowledge
of LC-3 assembly language?
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Very limited set of commands
Fixed length instructions
Limited addressing modes
Operands cannot be in memory
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The 68HC11 is CISC
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Full set of commands
Variable length instructions
Addressing modes
Operands can be in memory
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