Transcript 370 lectures - UWEC Computer Science Department

Apps
O/S
Arch
mArch
Hardware as Objects
Logic
Digital
Designing an Instruction Set
Analog
Devices
Physics
CS 352 : Computer Organization and Design
University of Wisconsin-Eau Claire
Dan Ernst
OO Design
• Encapsulation: the concept that data and functionality
go together into a single Object
• Encapsulation in programming:
– Private data members
– Operations on those data members
• Encapsulation in hardware:
– Data members (in registers)
– Operations on those data members (registers)
• What interface do we present to the “users”?
CS 352 : Computer Organization and Design
University of Wisconsin-Eau Claire
Dan Ernst
An Instruction to the Computer
Data: Let’s say we have 8 registers, numbered 0 7
(denoted: r0, r1, r2, …, r7)
Operation: What might we do to this data?
–
–
–
–
Add or Subtract (arithmetic)
Bitwise And / Or (logic)
Move it around
…
Put together, we can instruct the computer by saying something like:
“Add r3 to r4 and store the result in r6”
r6 = r4 + r3
All together, the collection of instructions is called the Instruction Set
CS 352 : Computer Organization and Design
University of Wisconsin-Eau Claire
Dan Ernst
Instruction Encoding
• Since the EDSAC (1949) almost all computers stored
program instructions the same way they store data.
– As bits
• Each instruction is encoded as a number
– Opcode field: what instruction to perform.
– Operand fields: what data to perform it on.
add
R1
R2
R3
011011
001
010
011
CS 352 : Computer Organization and Design
University of Wisconsin-Eau Claire
Dan Ernst
What If?
• …I wanted to do
r6 = r3 + r4 + r5 ?
CS 352 : Computer Organization and Design
University of Wisconsin-Eau Claire
Dan Ernst
Simplicity Favors Regularity
If you makes things regular, then things will be simple
•
Examples:
– all arithmetic operations must have 3 operands (2 source, 1 destination)
– all instructions must have the same size (i.e. # bytes)
– Register fields must be in the same place in all instruction formats
CS 352 : Computer Organization and Design
University of Wisconsin-Eau Claire
Dan Ernst
What If?
• …I wanted to do
r6 = r3 + r4 + r5 ?
r7 = r3 + r4
r6 = r7 + r5
• …I need to store more than 8 things?
CS 352 : Computer Organization and Design
University of Wisconsin-Eau Claire
Dan Ernst
Memory Storage
• Large array of storage accessed using memory addresses
– A machine with a 32 bit address can reference memory locations
0 to 232-1 (or 4,294,967,295)
– A machine with a 64 bit address can reference memory locations
0 to 264-1 (or 18,446,744,073,709,551,615)
• Lots of different ways to calculate the address.
CS 352 : Computer Organization and Design
University of Wisconsin-Eau Claire
Dan Ernst
What If?
• …I wanted to do
r6 = r3 + r4 + r5 ?
r7 = r3 + r4
r6 = r7 + r5
• …I need to store more than 8 things?
• …I want to perform an operation conditionally?
(Ok, there is a need for other kinds of instructions…)
CS 352 : Computer Organization and Design
University of Wisconsin-Eau Claire
Dan Ernst
Instruction Set Design
•
What instructions should be included?
– add, branch, load/store
– multiply, divide, sqrt
– mmx_add
•
What storage locations?
– How many registers?
– How much memory?
– Any other “architected” storage?
•
How should instructions be formatted?
– 0, 1, 2 or more operands?
• There are trade-offs to all of these decisions!
CS 352 : Computer Organization and Design
University of Wisconsin-Eau Claire
Dan Ernst
Why Study Instruction Set Design?
• Isn’t there only one?
– No, and even if there was it is too messy for a first course in computer
architecture.
• How often are new architectures created?
– Embedded processors are designed all the time.
– Even the x86 line changes (MMX, MMX2, SSE, etc.)
– Machines with special purpose/mutable instruction sets are becoming more
common
• Will I ever get to (have to) design one?
– Very possibly
CS 352 : Computer Organization and Design
University of Wisconsin-Eau Claire
Dan Ernst
Example Architectures
• MIPS
– 32 registers ( $0 - $31 )
– 32 bits in each register (called a word in MIPS-speak)
– Load/Store Architecture
• Intel 8086 (x86)
– 4 general purpose registers (ax, bx, cx, dx) 16 bits
• You can treat them as two 8 bits as well (for 8, 8-bit registers)
– 3 pointer registers (si,di,ip), 4 segment (cs,ds,ss,es),
2 stack (sp, bp), status register (flags)
CS 352 : Computer Organization and Design
University of Wisconsin-Eau Claire
Dan Ernst
Instruction Set Design
The LC2k7 Instruction Set
CS 352 : Computer Organization and Design
University of Wisconsin-Eau Claire
Dan Ernst
LC-2k7 Architecture
• 32-bit processor
– Instructions are 32 bits
– Integer registers are 32 bits
• 8 registers
• supports 65536 words of memory
• 8 instructions
– add, nand, lw, sw, beq, jalr, halt, noop
CS 352 : Computer Organization and Design
University of Wisconsin-Eau Claire
Dan Ernst
Assembly Format
• Format:
label <white> instr <white> field0 <white> field1 <white> field2 <white> comments
• Labels:
Max of 6 characters, starts with a letter {A..Z,a..z} followed by letters or numbers.
• Instructions:
add, nand, lw, sw, beq, jalr, noop, halt, and “.fill”
CS 352 : Computer Organization and Design
University of Wisconsin-Eau Claire
Dan Ernst
Simple LC2K7 Example
• f = (g + h) + (i + j); // C++ code
• Assume the result f is to be stored in register 5 and that
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–
–
–
•
r1  g
r2  h
r3  i
r4  j
The compiler might produce the following LC2K7 code :
add
add
add
5 1 2
6 3 4
5 6 5
# all R-type instructions
# format is: op dest, src1, src2
CS 352 : Computer Organization and Design
University of Wisconsin-Eau Claire
Dan Ernst
LC2K7 Arithmetic/Logic Instructions
•
•
•
•
Register type instructions (R-type)
1 operation (add, nand)
3 operands (destination, source1, source2)
Operands always listed in the same order
– simplicity favors regularity!
• All arithmetic occurs on data in registers
– no memory refs allowed!
CS 352 : Computer Organization and Design
University of Wisconsin-Eau Claire
Dan Ernst
Load/Store Architecture
•
Since all arithmetic occurs on data in regs, how do you put data from memory
into the regs in the first place?
•
Load/store: the only two instructions able to reference memory
•
LC2K7 (like MIPS) is a “load/store ISA”
•
LC uses base + displacement addressing
CS 352 : Computer Organization and Design
University of Wisconsin-Eau Claire
Dan Ernst
Load/Store Example
• g = h + A[8];
// A is an array
• Assume the result g is to be stored in register 1 and that
– r2  h
– r3  A (i.e. the base address: just like a pointer in C/C++)
• The compiler might produce the following LC2K7 code :
lw 4 3 8
add 1 2 4
# M[$r3 + 8]
# h + A[8]
CS 352 : Computer Organization and Design
University of Wisconsin-Eau Claire
Dan Ernst
Load/Store Details (1)
• lw (load word) and sw (store word) are I-type instructions
– I = immediate
• Address is computed by adding the base address + an offset
– The second field is the register # that holds the base address
– The third field is the offset amount (NOT a register!)
• LC2K7 uses word-addressable memory
– Each address holds 4 bytes (32 bits)
• MIPS uses byte-addressable memory
– Sequential word addresses differ by 4 (4 bytes per word)
CS 352 : Computer Organization and Design
University of Wisconsin-Eau Claire
Dan Ernst
Load/Store Details (2)
•
LC2K7 (like MIPS) is Big Endian
•
Big vs Little Endian: a term from “Gulliver’s Travels”
– Big Endian: address of data is the address of the MSByte
– Little Endian: address of data is the address of the LSByte (byte-swapped)
CS 352 : Computer Organization and Design
University of Wisconsin-Eau Claire
Dan Ernst
Load/Store Example (1)
• A[12] = h + A[6];
• Assume: r2  h, r3 A’s base address
• The compiler might produce the following LC code :
lw 1 3 6
add 1 2 1
sw 1 3 12
# whatever’s in r3 + 6
# same format for address as lw
• Note that sw has same format as lw, but different data transfer
interpretation (register is the source instead of the destination)
CS 352 : Computer Organization and Design
University of Wisconsin-Eau Claire
Dan Ernst
Load/Store Example (2)
• g = h + A[i];
// uses variable indexing!
• Assume: r2  h, r3  A, r4  i, and r5  g
• The compiler might produce the following LC code :
add
lw
add
1 3 4
6 1 0
5 6 2
# &A + i (the full address)
# load value at address just computed (plus 0)
• Note that there is no lw/sw instructions that use 2 registers to compute
the address!
CS 352 : Computer Organization and Design
University of Wisconsin-Eau Claire
Dan Ernst
Load/Store Example (3)
• g = h + Q;
// uses variable indexing!
• Assume: r2  h, r5  g, Q in memory
• Using labels, this can be done like so:
Q
lw
add
…
6 0 Q
5 6 2
.fill
42
CS 352 : Computer Organization and Design
University of Wisconsin-Eau Claire
# get what’s at label Q (offset 0)
Dan Ernst
Branch Example
if (i == j) {
f = g + h;
} else {
f = f + i;
}
•
Assume: r1  j; r2 f; r3  g; r4  h; r5  i
yes
after
beq
add
beq
add
…..
1
2
0
2
5
2
0
3
CS 352 : Computer Organization and Design
University of Wisconsin-Eau Claire
yes
5
after
4
# branch if r1 and r5 are equal
# branch if 0 == 0
Dan Ernst
PC-Relative Addressing
• Program Counter (PC): Register that holds the address of the
next instruction to be loaded from memory
• Variant on base + displacement
• Leave it to the assembler or even linker to determine the
immediate value, why?
CS 352 : Computer Organization and Design
University of Wisconsin-Eau Claire
Dan Ernst
Branch Example (revisited)
if (i == j) {
f = g + h;
} else {
f = f + i;
}
•
Assume: r1  j; r2 f; r3  g; r4  h; r5  i
yes
after
beq
add
beq
add
…..
1
2
0
2
5
2
0
3
CS 352 : Computer Organization and Design
University of Wisconsin-Eau Claire
2
5
1
4
# branch if r1 and r5 are equal
# branch if 0 == 0
Dan Ernst
Longer Assembly Example
start
done
five
neg1
stAddr
lw
lw
add
beq
beq
noop
halt
.fill
.fill
.fill
1 0 five
213
112
012
0 0 start
load reg1 with 5 (uses symbolic address)
load reg2 with -1 (uses numeric address)
decrement reg1
goto end of program when reg1 equals 0
go back to the beginning of the loop
end of program
5
-1
start
CS 352 : Computer Organization and Design
University of Wisconsin-Eau Claire
will contain the address of start (2)
Dan Ernst