Transcript Computer Architecture and Organization Miles Murdocca and

Chapter 4 - The Instruction Set Architecture
4-1
Computer Architecture and
Organization
Miles Murdocca and Vincent Heuring
Chapter 4 – The
Instruction Set
Architecture
Computer Architecture and Organization by M. Murdocca and V. Heuring
© 2007 M. Murdocca and V. Heuring
Chapter 4 - The Instruction Set Architecture
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Chapter Contents
4.1 Hardware Components of the Instruction Set Architecture
4.2 ARC, A RISC Computer
4.3 Pseudo-Operations
4.4 Synthetic Instructions
4.5 Examples of Assembly Language Programs
4.6 Accessing Data in Memory—Addressing Modes
4.7 Subroutine Linkage and Stacks
4.8 Input and Output in Assembly Language
4.9 Case Study: The Java Virtual Machine ISA
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Chapter 4 - The Instruction Set Architecture
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The Instruction Set Architecture
• The Instruction Set Architecture (ISA) view of a machine
corresponds to the machine and assembly language levels.
• A compiler translates a high level language, which is architecture
independent, into assembly language, which is architecture
dependent.
• An assembler translates assembly language programs into
executable binary codes.
• For fully compiled languages like C and Fortran, the binary codes
are executed directly by the target machine. Java stops the
translation at the byte code level. The Java virtual machine, which
is at the assembly language level, interprets the byte codes
(hardware implementations of the JVM also exist, in which Java
byte codes are executed directly.)
Computer Architecture and Organization by M. Murdocca and V. Heuring
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The System Bus Model of a Computer
System, Revisited
• A compiled program is copied from a hard disk to the memory. The
CPU reads instructions and data from the memory, executes the
instructions, and stores the results back into the memory.
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Chapter 4 - The Instruction Set Architecture
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Common Data Type Sizes
• A byte is composed of 8 bits. Two nibbles make up a byte.
• Halfwords, words, doublewords, and quadwords are composed of bytes
as shown below:
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Chapter 4 - The Instruction Set Architecture
Big-Endian and Little-Endian Formats
• In a byte-addressable machine, the smallest datum that can be
referenced in memory is the byte. Multi-byte words are stored as a
sequence of bytes, in which the address of the multi-byte word is the
same as the byte of the word that has the lowest address.
• When multi-byte words are used, two choices for the order in which
the bytes are stored in memory are: most significant byte at lowest
address, referred to as big-endian, or least significant byte stored at
lowest address, referred to as little-endian.
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Chapter 4 - The Instruction Set Architecture
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Memory Map for the ARC
• Memory
locations are
arranged linearly
in consecutive
order. Each
numbered
location
corresponds to
an ARC word.
The unique
number that
identifies each
word is referred
to as its
address.
Computer Architecture and Organization by M. Murdocca and V. Heuring
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Chapter 4 - The Instruction Set Architecture
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Example of ARC Memory Layout
• The table illustrates both the distinction between an address and the
data that is stored there, and the fact that ARC/SPARC is a big-endian
machine. The table shows four bytes stored at consecutive addresses
00001000 to 00001003.
• Thus the byte address 0x00001003 contains the byte 0xDD. Since this
is a big-endian machine (the big end is stored at the lowest address)
the word stored at address 0x00001000 is 0xAABBCCDD.
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Chapter 4 - The Instruction Set Architecture
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Abstract View of a CPU
• The CPU consists of a data section containing registers and an ALU,
and a control section, which interprets instructions and effects register
transfers. The data section is also known as the datapath.
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The Fetch-Execute Cycle
• The steps that the control unit carries out in executing a program are:
(1) Fetch the next instruction to be executed from memory.
(2) Decode the opcode.
(3) Read operand(s) from main memory, if any.
(4) Execute the instruction and store results, if any.
(5) Go to step 1.
This is known as the fetch-execute cycle.
Computer Architecture and Organization by M. Murdocca and V. Heuring
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An Example Datapath
• The ARC datapath is made up of a collection of registers known as the
register file and the arithmetic and logic unit (ALU).
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ARC User-Visible Registers
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ARC Assembly Language Format
• The ARC assembly language format is the same as the SPARC
assembly language format.
• This example shows the assembly language format for ARC (and
SPARC) arithmetic and logic instructions.
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ARC Load / Store Format
• This example shows the assembly language format for ARC load and
store instructions.
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Simple Example: Add Two Numbers
• The figure shows a simple program fragment using our ld, st, and
add instructions. This fragment is equivalent to the C statement:
z = x + y;
• Since ARC is a load-store machine, the code must first fetch the x and
y operands from memory using ld instructions, and then perform the
addition, and then store the result back into z using an st instruction.
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ARC Transfer of Control Sequence
• This example shows the assembly language format for ARC branch
instructions.
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ARC Fragment that Computes the
Absolute Value
• As an example of using the ARC instruction types we have seen so
far, consider the absolute value function, abs:
abs(x) := if (x < 0) then x = -x;
An ARC fragment to implement this is shown below:
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A Portion of the ARC ISA
• The ARC ISA is a subset of the SPARC ISA. A portion of the ARC ISA
is shown here.
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ARC Instruction and PSR Formats
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Chapter 4 - The Instruction Set Architecture
ARC Data
Formats
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ARC Pseudo-Ops
• Pseudo-ops are instructions to the assembler. They are not part of the
ISA, but instruct the assembler to do an operation at assembly time.
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Synthetic Instructions
• Many assemblers will accept synthetic instructions that are converted to
actual machine-language instructions during assembly. The figure
below shows some commonly used synthetic instructions.
• Synthetic instructions are single instructions that replace single
instructions, which are different from macros which are discussed later.
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ARC Example Program
• An ARC assembly language program adds two integers:
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A More
Complex
Example
Program
• An ARC program
sums five integers.
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One, Two, Three-Address Machines
• Consider how the C expression A = B*C + D might be evaluated by each
of the one, two, and three-address instruction types.
• Assumptions: Addresses and data words are two bytes in size. Opcodes
are 1 byte in size. Operands are moved to and from memory one word
(two bytes) at a time.
• Three-Address Instructions: In a three-address instruction, the
expression A = B*C + D might be coded as:
mult
B, C, A
add
D, A, A
which means multiply B by C and store the result at A. (The mult and
add operations are generic; they are not ARC instructions.) Then, add D
to A and store the result at address A. The program size is 72 = 14
bytes. Memory traffic is 14 + 2(23) = 26 bytes.
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One, Two, Three-Address Machines
• Two Address Instructions: In a two-address instruction, one of the
operands is overwritten by the result. Here, the code for the expression
A = B*C + D is:
load
B, A
mult
C, A
add
D, A
The program size is now 3(1+22) or 15 bytes. Memory traffic is 15 +
22 + 223 or 31 bytes.
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One, Two, Three-Address Machines
• One Address (Accumulator) Instructions: A one-address instruction
employs a single arithmetic register in the CPU, known as the
accumulator. The code for the expression A = B*C + D is now:
load
B
mult
C
add
D
store A
The load instruction loads B into the accumulator, mult multiplies C by
the accumulator and stores the result in the accumulator, and add does
the corresponding addition. The store instruction stores the
accumulator in A. The program size is now 34 or 12 bytes, and memory
traffic is 12 + 42 or 20 bytes.
Computer Architecture and Organization by M. Murdocca and V. Heuring
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Chapter 4 - The Instruction Set Architecture
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Addressing Modes
• Four ways of computing the address of a value in memory: (1) a constant
value known at assembly time, (2) the contents of a register, (3) the sum
of two registers, (4) the sum of a register and a constant. The table gives
names to these and other addressing modes.
Computer Architecture and Organization by M. Murdocca and V. Heuring
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Chapter 4 - The Instruction Set Architecture
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Subroutine Linkage – Registers
• Subroutine linkage with registers passes parameters in registers.
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Chapter 4 - The Instruction Set Architecture
Subroutine Linkage – Data Link Area
• Subroutine linkage with a data link area passes parameters in a
separate area in memory. The address of the memory area is passed
in a register (%r5 here).
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Subroutine Linkage – Stack
• Subroutine linkage with a stack passes parameters on a stack.
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Chapter 4 - The Instruction Set Architecture
Stack
Linkage
Example
• A C program
illustrates nested
function calls.
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Chapter 4 - The Instruction Set Architecture
Stack
Linkage
Example
(cont’)
• (a-f) Stack
behavior during
execution of the
program shown in
previous slide.
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Chapter 4 - The Instruction Set Architecture
Stack
Linkage
Example
(cont’)
• (g-k) Stack behavior
during execution of
the C program
shown previously.
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Chapter 4 - The Instruction Set Architecture
Input and
Output for
the ISA
• Memory map for
the ARC, showing
memory mapped
I/O.
Computer Architecture and Organization by M. Murdocca and V. Heuring
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Touchscreen I/O Device
• A user selecting an object on a touchscreen:
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Chapter 4 - The Instruction Set Architecture
Flowchart for I/O
Device
• Flowchart illustrating the control
structure of a program that tracks
a touchscreen.
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Chapter 4 - The Instruction Set Architecture
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Java Virtual Machine Architecture
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Chapter 4 - The Instruction Set Architecture
Java
Program
and
Compiled
Class
File
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Chapter 4 - The Instruction Set Architecture
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A Java Class File
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Chapter 4 - The Instruction Set Architecture
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A Java Class File (Cont’)
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Chapter 4 - The Instruction Set Architecture
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Byte Code for Java Program
• Disassembled byte code for previous Java program.
Location
0x00e3
0x00e4
0x00e5
0x00e6
0x00e7
0x00e8
0x00e9
0x00ea
0x00eb
0x00ec
0x00ed
0x00ee
0x00ef
Code
0x10
0x0f
0x3c
0x10
0x09
0x3d
0x03
0x3e
0x1b
0x1c
0x60
0x3e
0xb1
Mnemonic
bipush
15
istore_1
bipush
9
istore_2
iconst_0
istore_3
iload_1
iload_2
iadd
istore_3
return
Computer Architecture and Organization by M. Murdocca and V. Heuring
Meaning
Push next byte onto stack
Argument to bipush
Pop stack to local variable 1
Push next byte onto stack
Argument to bipush
Pop stack to local variable 2
Push 0 onto stack
Pop stack to local variable 3
Push local variable 1 onto stack
Push local variable 2 onto stack
Add top two stack elements
Pop stack to local variable 3
Return
© 2007 M. Murdocca and V. Heuring