Transcript Destination register (%r1)

ITEC 352
Lecture 20
JVM Intro
Review
• Questions?
• Project due today
• Activation record
– How is it used?
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Outline
• Functions in assembly
• Intro to JVM
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Java Virtual Machine Architecture
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A Java Class
File
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A Java Class
File (2)
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A Java Class File (Cont’)
bipush: push into stack
Istore_1: pop the top of the
stack and store the value in local
variable at index “1”.
Background: local variables are
converted into array indices.
iload_1: push the value at array
index 1 into stack.
0
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Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
Byte Code
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Mnemonic
bipush
15
istore_1
bipush
9
istore_2
iconst_0
istore_3
iload_1
iload_2
iadd
istore_3
return
Meaning
Push next byte onto stack
Argument to bipush
Pop stack to local variable 1
Push next byte onto stack
Argument to bipush
Pop stack to local variable 2
Push 0 onto stack
Pop stack to local variable 3
Push local variable 1 onto stack
Push local variable 2 onto stack
Add top two stack elements
Pop stack to local variable 3
Return
Assembly
process
• Translation of Assembly code into Machine
language.
• Recall:
– Every assembly instruction is represented as a 32 bit
machine instruction.
– Since there are different types of assembly
instructions (e.g., arithmetic instructions, branch
instructions etc.),
• There are also different way of using the 32 bits to represent
machine instructions.
– These different ways of packing 32 bits of machine
code are called Instruction formats.
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Examples
• Consider the following two usages of the load (ld) instruction:
ld [x], %r1
Meaning: Load from a memory address specified as a constant value
(in this case x) plus the contents of register %r0 into register %r1.
ld %r1, %r2, %r3
Meaning: Load from memory address obtained by adding the values of
registers %r1 and %r2 into the register %r3
In the first instruction we are using a constant value (memory
address x). Whereas in the second we are using registers.
Hence, there are two memory instruction formats in
Machine code. (on next slide)
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Memory instruction formats in machine code
Instruction ld %r1, %r2, %r3 is represented as follows:
rd: Destination register (%r3) ; op3: ld (11),
rs1: first source register (%r1), rs2: second source register.
Instruction ld [x], %r1 is represented as follows:
rd: Destination register (%r1) ; op3: ld (11),
rs1: first source register (%r0 ) (Here, %r0 is assumed to be there implicitly)
simm13: address “x”. This should fit into 13 bits.
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Complete ARC Instruction and PSR Formats
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Principles of Computer Architecture by M. Murdocca and V. Heuring
© 1999 M. Murdocca and V. Heuring
Assembly to machine code translation
• Given an instruction:
ld [x], %r1
The assembly process pattern matches this
instruction with machine formats to
obtain the machine code.
E.g., After it sees the instruction, it maps it to
the second memory format (the one with
simm13).
It then converts the instruction as follows:
ld
op3: 11 (op3 = 11)
[x]
simm13: Memory address x. If .org 2048, then x = 2048. In binary =
010000000000
%r0
rs1 ( source register) (address = 00000) 5 bits to address a register.
%r1
rd (destination register) (address = 00001)
Other fields: In the previous slide, notice that there is an “i” field to distinguish
between the two memory formats. Here, i = 1.
Assembledcod
e.
ld: opcode: 11
rd: destination register: 000`1
op3: 000000
rs1:
00000
i: 1
This is the instruction we just looked at. The right side represents machine code.
ld [x], %r1
1100 0010 0000 0000 0010 1000 0001 0100
These are some other assembled instructions.
ld [y], %r2
1100 0100 0000 0000 0010 1000 0001 1000
addcc %r1,%r2,%r3 1000 0110 1000 0000 0100 0000 0000 0010
st %r3, [z]
1100 0110 0010 0000 0010 1000 0001 1100
jmpl %r15+4, %r0
15
9
1000 0001 1100 0011 1110 0000 0000 0100
0000 0000 0000 0000 0000 0000 0000 1111
0000 0000 0000 0000 0000 0000 0000 1001
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Next.
• We just looked at how to convert
Assembly into Machine code.
• Next: We will briefly look at the steps to
convert a high level program into
assembly.
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Summary
so far …
• We looked at
– Stages of a compiler (briefly)
– Assembly instructions
– Translating assembly into machine code …
• Next: speeding up processing …
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CPU
Performanc
e
• E.g., will a 4.1 Ghz CPU be faster than a
2.0 Ghz CPU?
– So is the CPU cycle time a measure of
performance?
• How about amount of cache?
• Anything else?
• Next: performance due to pipelining.
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Pipelining
Speeding up the computation process
Complex and Reduced Instruction Sets:
Complex Instruction Set Computer (CISC)
Reduced Instruction Set Computer (RISC)
Next: the differences?
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CISC Vs.
RISC
• A long time back when memory costed
– The focus of most computer architects
• (E.g., Intel and Motorola)
• Support fewer instructions that performed more complicated computations.
• E.g., addld [a], [b], [c] would be a complex instruction that replaced:
ld [a], %r1
ld [b], %r2
addcc %r1, %r2, %r3
st %r3, [c]
Why?
Complex instructions  Shorter programs  Smaller
memory needed.
However, memory became cheaper. So architects started
thinking about techniques to use more memory that
would speed up computations.
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Review
• JVM + Bytecode
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