Transcript chapter one transparency

The 68HC11 Microcontroller
Chapter 1: Introduction to 68HC11
The 68HC11 Microcontroller
H. Huang Transparency No.1-1
The 68HC11 Microcontroller
PULSE ACCUMULATOR
O
C
1
RAM-256 bytes
PERIODIC INTERRUPT
EEP ROM-512 bytes
COP WATCHDOG
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
SS
SCK
MOSI
SP I
P ORT
E
PAI
OC2
OC3
OC4
OC5
IC1
IC2
IC3
MISO
A/D
CONVERTER
TxD
SCI
RxD
PA0
PD1
PD0
M68HC11 CP U
RESET
ADDRESS DATA BUS
INTERRUP TS
IRQ
HANDSHAKE I/O
(VPPB ULK)
DATA DIRECTION C
XTAL
EXTAL
PD5
PD4
PD3
PD2
PORT
D
VREF H
VREF L
XIRQ
PA7
PA6
PA5
PA4
PA3
PA2
PA1
P ORT
A
DATA DIRECTION
ROM-8KB
OSCILLATOR
P ORT B
P ORT C
PARALLEL
I/O
E
MODA
LIR
MODB
(V STBY)
VD D
VSS
MODE
SELECT
P OWER
P P P P P P P P
B B B B B B B B
7 6 5 4 3 2 1 0
P P P P P P P P S S
C C C C C C C C T T
7 6 5 4 3 2 1 0 R R
B A
AA AA AA AA A A AA AA AA
1 1 1 1 1 1 9 8 D D DD DD DD
5 4 3 2 1 0
7 6 5 4 3 2 1 0
R/W AS
SINGLE
CHIP
EXPAND
Figure 1.2 68HC11A8 block diagram (redrawn with permission of Motorola)
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The 68HC11 Microcontroller
7
Accumulator A
0 7
Accumulator B
0 A:B
15
Double Accumulator D
0 D
15
Index Register IX
0 IX
15
Index Register IY
0 IY
15
Stack pointer
0 SP
15
P rogram Counter
0 PC
S
X
H
I
N
Z
V
C CCR
Carry
Overflow
Zero
Negative
I interrupt mask
Half-Carry (from bit 3)
X Interrupt Mask
Stop Disable
Figure 1.3 MC68HC11 P rogrammer's model
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The 68HC11 Microcontroller
Memory Addressing
Memory consists of addressable locations
A memory location has 2 components: address and contents
address
contents
Data transfer between CPU and memory involves address
bus and data bus
address bus lines
CPU
memory
data bus lines
Figure 1.5 Data transfer between CPU and memory
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The 68HC11 Microcontroller
68HC11 addressing modes
Table 1.1 Prefix for number representation
Base
binary
octal
decimal
hexadecimal
Prefix
%
@
nothing*
$
*Note: Some assemblers use &
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The 68HC11 Microcontroller
ADDRESSING
MODES
Operands needed in an instruction are specified by one of the 6
addressing modes
Immediate mode
Direct mode
Extended mode
Indexed mode
Inherent mode
Relative mode
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The 68HC11 Microcontroller
Immediate mode
The actual operand is contained in the byte or bytes immediately following the
instruction opcode
LDAA #22
ADDA #@32
LDD #1000
Note that the (#) is a critical assembler directive!
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The 68HC11 Microcontroller
Direct mode
A one-byte value is used as the address of a memory operand (located in on-chip SRAM)
ADDA $10
SUBA $20
LDD $30
Extended mode
A two-byte value is used as the address of a memory operand
LDAA $1000
LDX $1000
ADDD $1030
Indexed mode
The sum of one of the index registers and an 8-bit value is used as the address of a
memory operand
ADDA 10,X
LDAA 3,Y
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The 68HC11 Microcontroller
Inherent mode
-
Operands are implied by the instruction
No address information is needed
ABA
INCB
INX
Relative mode
-
Used in branch instructions to specify the branch target
Specified using either a 16-bit value or a label (preferred)
...
BEQ there
ADDA #10
...
there DECB
H. Huang Transparency No.1-9
The 68HC11 Microcontroller
A Sample of 68HC11 Instructions
The LOAD instructions
A group of instructions that place a value or copy the contents of a memory
location (or locations) into a register
LDAA
LDAB
LDD
LDX
LDY
LDS
<opr> Load Accumulator A
<opr> Load Accumulator B
<opr> Load Double Accumulator D
<opr> Load Index Register X
<opr> Load Index Register Y
<opr> Load Stack Pointer
<opr> can be immediate, direct, extended, or index mode
Examples
LDAA $10
LDX #$1000
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The 68HC11 Microcontroller
The ADD instruction
A group of instructions perform addition operation
ABA
ABX
ABY
ADDA
ADDB
ADDD
ADCA
ADCB
<opr>
<opr>
<opr>
<opr>
<opr>
<opr> is specified using immediate, direct, extended, or index mode
Examples.
ADDA #10
ADDA $20
ADDD $30
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The 68HC11 Microcontroller
The SUB instruction
A group of instructions that perform the subtract operation
SBA
SUBA
SUBB
SUBD
SBCA
SBCB
<opr>
<opr>
<opr>
<opr>
<opr>
; A  [A] - <opr> - C flag
; A  [B] - <opr> - C flag
<opr> can be immediate, direct, extended, or index mode
Examples
SUBA
SUBA
SUBA
SUBD
#10
$10
0,X
10,X
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The 68HC11 Microcontroller
The STORE instruction
A group of instructions that store the contents of a register into
a memory location or memory locations
STAA
STAB
STD
STX
STY
STS
<addr>
<addr>
<addr>
<addr>
<addr>
<addr>
<addr> can be direct, extended, or index mode
Examples:
STAA
STAA
STD
STD
STD
$20
10,X
$10
$1000
0,X
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The 68HC11 Microcontroller
The 68HC11 Machine Code
A 68HC11 instruction consists of 1 to 2 bytes of opcode and 0 to 3 bytes of
operand information
Examples
Assembly instruction
LDAA #29
STAA $00
ADDA $02
STAA $01
INY
Machine instructions
(in hex format)
86 1D
97 00
9B 02
97 01
18 08
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The 68HC11 Microcontroller
Decoding machine language instructions
Procedure
Step 1 Compare the first one or two bytes with the opcode table to identify the
corresponding assembly mnemonic and format.
Step 2 Identify the operand bytes after the opcode field.
Step 3 Write down the corresponding assembly instruction.
Step 4 Repeat step 1 to 3 until the machine code file is exhausted.
A sample of machine codes and assembly instruction format
machine code
01
86
96
C6
D6
CC
DC
8B
9B
CB
assembly instruction format
NOP
LDAA IMM
LDAA DIR
LDAB IMM
LDAB DIR
LDD IMM
LDD DIR
ADDA IMM
ADDA DIR
ADDB IMM
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The 68HC11 Microcontroller
machine code
DB
C3
D3
97
D7
DD
assembly instruction format
ADDB DIR
ADDD IMM
ADDD DIR
STAA DIR
STAB DIR
STD DIR
Example. Disassemble the following machine code to its corresponding assembly
instructions.
96 30 8B 07 97 30 96 31
Solution:
The disassembly process starts from the leftmost byte. We next look up
the machine code table to see which instruction it corresponds to.
Instruction 1.
Step 1. The first byte 96 corresponds to the instruction LDAA DIR.
Step 2. The second byte, 30, is the direct address.
Step 3. Therefore, the first instruction is LDAA $30.
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The 68HC11 Microcontroller
Instruction 2.
Step 1. The third byte (8B) corresponds to the instruction ADDA IMM.
Step 2. The immediate value is 07.
Step 3. Therefore, the second instruction is ADDA $07.
Instruction 3.
Step 1. The fifth byte (97) corresponds to the instruction STAA DIR.
Step 2. The DIR address is the next byte 30.
Step 3. Therefore, the third instruction is STAA $30.
Instruction 4.
Step 1. The seventh byte (96) corresponds to the instruction LDAA DIR.
Step 2. The DIR value is the next byte 31.
Step 3. Therefore, the four instruction is LDAA $31.
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The 68HC11 Microcontroller
machine code assembly instruction format
01
86
96
C6
D6
CC
DC
8B
9B
CB
DB
C3
D3
97
D7
DD
NOP
LDAA IMM
LDAA DIR
LDAB IMM
LDAB DIR
LDD IMM
LDD DIR
ADDA IMM
ADDA DIR
ADDB IMM
ADDB DIR
ADDD IMM
ADDD DIR
STAA DIR
STAB DIR
STD DIR
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The 68HC11 Microcontroller
The 68HC11 Instruction Execution Cycle
-
-
Perform a sequence of read cycles to fetch instruction opcode byte and address
information.
Optionally perform read cycle(s) required to fetch the memory operand.
Perform the operation specified by the opcode.
Optionally write back the result to a register or a memory location.
-
Consider the following 3 instructions
Assembly instruction Memory location Opcode
LDAA $2000
ADAA $3000
STAA $2000
$C000
$C003
$C006
B6 20 00
BB 30 00
B7 20 00
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The 68HC11 Microcontroller
Instruction LDAA $2000
Step 1. Place the value in PC on the address bus with a request to read the contents of that
location.
Step 2. The opcode byte $B6 at $C000 is returned to the CPU and PC is incremented by 1.
Memory contents
Address
$B6
$C000
$20
$C001
$00
$C002
$BB
$C003
$30
$C004
$00
$C005
$B7
$C006
$20
$C007
$00
$C008
Address bus
$C000
CP U
$B6
Data bus
Before
After
$C000
$C001
PC
PC
Figure 1.10 Instruction 1--Opcode read cycle
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The 68HC11 Microcontroller
Step 3. CPU performs two read cycles to obtain the extended address $2000 from locations
$C001 and $C002. At the end the value of PC is incremented to $C003
Memory contents Address
Memory contents Address
Address bus
Address bus
$B6
$C000
$C001
$20
$C001
$00
$C002
$00
$C002
$BB
$C003
$BB
$C003
$30
$C004
$30
$C004
$00
$C005
$00
$C005
$20
$B7
$C006
$00
$B7
$C006
Data bus
$20
$C007
Data bus
$20
$C007
$00
$C008
$00
$C008
$C001
CP U
$B6
$C000
$20
$C002
CP U
Before
After first read
After second read
$C001
$C002
$C003
PC
PC
PC
Figure 1.11 Instruction 1--address byte read cycles
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The 68HC11 Microcontroller
Step 4. The CPU performs another read to get the contents of the memory location at
$2000, which is $19. The value $19 will be loaded into accumulator A.
Memory contents
Address
$19
$2000
Address bus
$2000
.
.
.
CPU
$37
$3000
$19
Data bus
Figure 1.12 Instruction 1--execution read cycle
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