Transcript ch01

The 68HC11 Microcontroller
Chapter 1: Introduction to 68HC11
The 68HC11 Microcontroller
Han-Way Huang
Minnesota State University, Mankato
H. Huang Transparency No.1-1
The 68HC11 Microcontroller
What is a computer?
Software
Hardware
Computer Hardware Organization
Control
unit
common bus
Arithmetic
logic
unit
memory
Registers
program
data
storage
storage
output
input
unit
unit
Figure 1.1 Computer hardware organization
H. Huang Transparency No.1-2
The 68HC11 Microcontroller
The processor
Registers -- storage locations in the processor
Arithmetic logic unit
Control unit
program counter keeps track of the address of the next instruction to be executed
status register flags the instruction execution result
The microprocessor
A processor implemented on a very large scale integration (VLSI) chip
Peripheral chips are needed to construct a product
The Microcontroller
The processor and peripheral functions implemented on one VLSI chip
H. Huang Transparency No.1-3
The 68HC11 Microcontroller
Features of the 68HC11A8 microcontroller
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8-bit CPU
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256 bytes SRAM
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512 bytes EEPROM
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8 KB ROM
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3 input capture channels
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5 output compare functions
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one 8-bit pulse accumulator
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one serial communication interface (SCI)
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one serial peripheral interface (SPI)
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real-time interrupt (RTI) circuit
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8-channel 8-bit A/D converter
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computer operate properly (COP) watchdog system
H. Huang Transparency No.1-4
The 68HC11 Microcontroller
P ULSE ACCUMULAT OR
O
C
1
RAM-256 bytes
P ERIODIC INT ERRUP T
EEPROM-512 bytes
COP WAT CHDOG
P E7
P E6
P E5
P E4
P E3
P E2
P E1
P E0
SS
SCK
MOSI
SPI
PORT
E
MISO
A/D
CONVERTER
T xD
SCI
RxD
VREFH
VREFL
PORT
A
P A0
P ORT
D
P D5
P D4
P D3
P D2
P D1
P D0
ADDRESS DATA BUS
INTERRUPTS
IRQ
HANDSHAKE I/O
(VPPBULK )
DAT A DIRECT ION C
XT AL
EXT AL
P A7
P A6
P A5
P A4
P A3
P A2
P A1
M68HC11 CPU
RESET
XIRQ
P AI
OC2
OC3
OC4
OC5
IC1
IC2
IC3
DATA DIRECTION
ROM-8KB
OSCILLATOR
PORT B
PORT C
P ARALLEL
I/O
E
MODA
LIR
MODB
(VSTBY)
VDD
VSS
MODE
SELECT
POWER
P P P P P P P P
B B B B B B B B
7 6 5 4 3 2 1 0
P P P P P P P P S S
C C C C C C C C T T
7 6 5 4 3 2 1 0 R R
B A
AA AA AA AA A A AA AA AA
1 1 1 1 1 1 9 8 D D DD DD DD
5 4 3 2 1 0
7 6 5 4 3 2 1 0
R/W AS
SINGLE
CHIP
EXP AND
Figure 1.2 68HC11A8 block diagram (redrawn with permission of Motorola)
H. Huang Transparency No.1-5
The 68HC11 Microcontroller
Examples of microcontroller applications
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Displays
Printers
Keyboards
Modems
Charge card phones
Refrigerators
Washing machines
Microwave ovens
Automobile engine fuel injection
Fax machines
Motor speed control
etc.
H. Huang Transparency No.1-6
The 68HC11 Microcontroller
Semiconductor memory
- Random-access memory (RAM): same amount of time
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is required to access any location on the same chip
Read-only memory (ROM): can only be read but not
written by the processor
Random-access memory
- Dynamic random-access memory (DRAM): periodic
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refresh is required to maintain the contents of a DRAM chip
Static random-access memory (SRAM): no periodic
refresh is required
Read-only memory
- Mask-programmed read-only memory (MROM):
programmed when being manufactured
- Programmable read-only memory (PROM): the memory
chip can be programmed by the end user
H. Huang Transparency No.1-7
The 68HC11 Microcontroller
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Erasable programmable ROM (EPROM)
1. electrically programmable many times
2. erased by ultraviolet light (through a window)
3. erasable in bulk (whole chip in one erasure operation)
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Electrically erasable programmable ROM (EEPROM)
1. electrically programmable many times
2. electrically erasable many times
3. can be erased one location, one row, or whole chip in one operation
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Flash memory
1. electrically programmable many times
2. electrically erasable many times
3. can only be erased in bulk
H. Huang Transparency No.1-8
The 68HC11 Microcontroller
Computer software
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Computer programs are known as software
A program is a sequence of instructions
Machine instruction
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A sequence of binary digits which can be executed by the processor
Hard to understand for human being
Assembly language
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Defined by assembly instructions
An assembly instruction is a mnemonic representation of a machine
instruction
Assembly programs must be translated before it can be executed -translated by an assembler
H. Huang Transparency No.1-9
The 68HC11 Microcontroller
High-level language
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Syntax of a high-level language is similar to English
A translator is required to translate the program written in a
high-level language -- done by a compiler
Source code
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A program written in assembly or high-level language
Object code
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The output of an assembler or compiler
H. Huang Transparency No.1-10
The 68HC11 Microcontroller
7
Accumulator A
0 7
Accumulator B
0 A:B
15
Double Accumulator D
0 D
15
Index Register IX
0 IX
15
Index Register IY
0 IY
15
Stack pointer
0 SP
15
Program Counter
0 PC
S
X
H
I
N
Z
V
C CCR
Carry
Overflow
Zero
Negative
I interrupt mask
Half-Carry (from bit 3)
X Interrupt Mask
Stop Disable
Figure 1.3 MC68HC11 Programmer's model
H. Huang Transparency No.1-11
The 68HC11 Microcontroller
Memory Addressing
Memory consists of addressable locations
A memory location has 2 components: address and contents
address
contents
Data transfer between CPU and memory involves address
bus and data bus
address bus lines
CPU
memory
data bus lines
Figure 1.5 Data transfer between CPU and memory
H. Huang Transparency No.1-12
The 68HC11 Microcontroller
68HC11 addressing modes
Table 1.1 Prefix for number representation
Base
binary
octal
decimal
hexadecimal
Prefix
%
@
nothing*
$
*Note: Some assemblers use &
Operands needed in an instruction are specified by one of the 6
addressing modes
Immediate mode
The actual operand is contained in the byte or bytes immediately following the
instruction opcode
LDAA #22
ADDA #@32
LDD #1000
H. Huang Transparency No.1-13
The 68HC11 Microcontroller
Direct mode
A one-byte value is used as the address of a memory operand (located in on-chip SRAM)
ADDA $10
SUBA $20
LDD $30
Extended mode
A two-byte value is used as the address of a memory operand
LDAA $1000
LDX $1000
ADDD $1030
Indexed mode
The sum of one of the index registers and an 8-bit value is used as the address of a
memory operand
ADDA 10,X
LDAA 3,Y
H. Huang Transparency No.1-14
The 68HC11 Microcontroller
Inherent mode
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Operands are implied by the instruction
No address information is needed
ABA
INCB
INX
Relative mode
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Used in branch instructions to specify the branch target
Specified using either a 16-bit value or a label (preferred)
...
BEQ there
ADDA #10
...
there DECB
H. Huang Transparency No.1-15
The 68HC11 Microcontroller
A Sample of 68HC11 Instructions
The LOAD instructions
A group of instructions that place a value or copy the contents of a memory
location (or locations) into a register
LDAA
LDAB
LDD
LDX
LDY
LDS
<opr>
<opr>
<opr>
<opr>
<opr>
<opr>
<opr> can be immediate, direct, extended, or index mode
Examples
LDAA $10
LDX #$1000
H. Huang Transparency No.1-16
The 68HC11 Microcontroller
The ADD instruction
A group of instructions perform addition operation
ABA
ABX
ABY
ADDA
ADDB
ADDD
ADCA
ADCB
<opr>
<opr>
<opr>
<opr>
<opr>
<opr> is specified using immediate, direct, extended, or index mode
Examples.
ADDA #10
ADDA $20
ADDD $30
H. Huang Transparency No.1-17
The 68HC11 Microcontroller
The SUB instruction
A group of instructions that perform the subtract operation
SBA
SUBA
SUBB
SUBD
SBCA
SBCB
<opr>
<opr>
<opr>
<opr>
<opr>
; A  [A] - <opr> - C flag
; A  [B] - <opr> - C flag
<opr> can be immediate, direct, extended, or index mode
Examples
SUBA
SUBA
SUBA
SUBD
#10
$10
0,X
10,X
H. Huang Transparency No.1-18
The 68HC11 Microcontroller
The STORE instruction
A group of instructions that store the contents of a register into
a memory location or memory locations
STAA
STAB
STD
STX
STY
STS
<addr>
<addr>
<addr>
<addr>
<addr>
<addr>
<addr> can be direct, extended, or index mode
Examples:
STAA
STAA
STD
STD
STD
$20
10,X
$10
$1000
0,X
H. Huang Transparency No.1-19
The 68HC11 Microcontroller
The 68HC11 Machine Code
A 68HC11 instruction consists of 1 to 2 bytes of opcode and 0 to 3 bytes of
operand information
Examples
Assembly instruction
LDAA #29
STAA $00
ADDA $02
STAA $01
INY
Machine instructions
(in hex format)
86 1D
97 00
9B 02
97 01
18 08
H. Huang Transparency No.1-20
The 68HC11 Microcontroller
Decoding machine language instructions
Procedure
Step 1 Compare the first one or two bytes with the opcode table to identify the
corresponding assembly mnemonic and format.
Step 2 Identify the operand bytes after the opcode field.
Step 3 Write down the corresponding assembly instruction.
Step 4 Repeat step 1 to 3 until the machine code file is exhausted.
A sample of machine codes and assembly instruction format
machine code
01
86
96
C6
D6
CC
DC
8B
9B
CB
assembly instruction format
NOP
LDAA IMM
LDAA DIR
LDAB IMM
LDAB DIR
LDD IMM
LDD DIR
ADDA IMM
ADDA DIR
ADDB IMM
H. Huang Transparency No.1-21
The 68HC11 Microcontroller
machine code
DB
C3
D3
97
D7
DD
assembly instruction format
ADDB DIR
ADDD IMM
ADDD DIR
STAA DIR
STAB DIR
STD DIR
Example. Disassemble the following machine code to its corresponding assembly
instructions.
96 30 8B 07 97 30 96 31
Solution:
The disassembly process starts from the leftmost byte. We next look up
the machine code table to see which instruction it corresponds to.
Instruction 1.
Step 1. The first byte 96 corresponds to the instruction LDAA DIR.
Step 2. The second byte, 30, is the direct address.
Step 3. Therefore, the first instruction is LDAA $30.
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The 68HC11 Microcontroller
Instruction 2.
Step 1. The third byte (8B) corresponds to the instruction ADDA IMM.
Step 2. The immediate value is 07.
Step 3. Therefore, the second instruction is ADDA $07.
Instruction 3.
Step 1. The fifth byte (97) corresponds to the instruction STAA DIR.
Step 2. The DIR address is the next byte 30.
Step 3. Therefore, the third instruction is STAA $30.
Instruction 4.
Step 1. The seventh byte (96) corresponds to the instruction LDAA DIR.
Step 2. The DIR value is the next byte 31.
Step 3. Therefore, the four instruction is LDAA $31.
H. Huang Transparency No.1-23
The 68HC11 Microcontroller
machine code assembly instruction format
01
86
96
C6
D6
CC
DC
8B
9B
CB
DB
C3
D3
97
D7
DD
NOP
LDAA IMM
LDAA DIR
LDAB IMM
LDAB DIR
LDD IMM
LDD DIR
ADDA IMM
ADDA DIR
ADDB IMM
ADDB DIR
ADDD IMM
ADDD DIR
STAA DIR
STAB DIR
STD DIR
H. Huang Transparency No.1-24
The 68HC11 Microcontroller
The 68HC11 Instruction Execution Cycle
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Perform a sequence of read cycles to fetch instruction opcode byte and address
information.
Optionally perform read cycle(s) required to fetch the memory operand.
Perform the operation specified by the opcode.
Optionally write back the result to a register or a memory location.
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Consider the following 3 instructions
Assembly instruction Memory location Opcode
LDAA $2000
ADAA $3000
STAA $2000
$C000
$C003
$C006
B6 20 00
BB 30 00
B7 20 00
H. Huang Transparency No.1-25
The 68HC11 Microcontroller
Instruction LDAA $2000
Step 1. Place the value in PC on the address bus with a request to read the contents of that
location.
Step 2. The opcode byte $B6 at $C000 is returned to the CPU and PC is incremented by 1.
Memory contents
Address
$B6
$C000
$20
$C001
$00
$C002
$BB
$C003
$30
$C004
$00
$C005
$B7
$C006
$20
$C007
$00
$C008
Address bus
$C000
CPU
$B6
Data bus
Before
After
$C000
$C001
PC
PC
Figure 1.10 Instruction 1--Opcode read cycle
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The 68HC11 Microcontroller
Step 3. CPU performs two read cycles to obtain the extended address $2000 from locations
$C001 and $C002. At the end the value of PC is incremented to $C003
Memory contents
Memory contents
Address
Address
Address bus
Address bus
$B6
$C000
$C001
$20
$C001
$00
$C002
$00
$C002
$BB
$C003
$BB
$C003
$30
$C004
$30
$C004
$00
$C005
$00
$C005
$20
$B7
$C006
$00
$B7
$C006
Data bus
$20
$C007
Data bus
$20
$C007
$00
$C008
$00
$C008
$C001
CPU
$B6
$C000
$20
$C002
CPU
Before
After first read
After second read
$C001
$C002
$C003
PC
PC
PC
Figure 1.11 Instruction 1--address byte read cycles
H. Huang Transparency No.1-27
The 68HC11 Microcontroller
Step 4. The CPU performs another read to get the contents of the memory location at
$2000, which is $19. The value $19 will be loaded into accumulator A.
Memory contents
Address
Address bus
$2000
$19
$2000
.
.
.
CPU
$37
$3000
$19
Data bus
Figure 1.12 Instruction 1--execution read cycle
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