Transcript ppt - Computer Science and Engineering

The Mobile Phone
Dr. Miguel A. Labrador
Department of Computer Science & Engineering
[email protected]
http://www.csee.usf.edu/~labrador
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Outline
• Hardware architecture
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Processor
Digital signal processors
Memory
Future trends and challenges
• Software architecture
– Three software layers
– The Java virtual machine
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Hardware Architecture
• Microprocessor, digital signal processors, memory, battery and
power control module, radio frequency (RF) interfaces, and
peripherals, such as keyboard, speakers, microphone, and display
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Microprocessor
• Dominated by Advanced RISC Machines (ARM)
– Manufactured by ARM Limited
– Also built by other companies that license the architecture
• Very low power consumption
• Most recent families includes the ARM9, ARM11 and Cortex
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The ARM9 Microprocessor
• ARM9 is a general purpose 32 bit architecture
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16KB cache for instructions
16 KB cache for data
Memory management unit
Typical computing power of 200 MIPS at 180 MHz
Includes some enhanced DSP extensions
• The ARM9E also supports Jazelle, a technology that allows
Java bytecode to be executed directly
– Higher performance than Java virtual machine
– Reduces power consumption by 80%
• Popular devices using this microprocessor
– Nintendo DS, SUN SPOT WSN device, Sony-Ericsson cellular
phones
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The ARM11 Microprocessor
• ARM11 is a general purpose 32 bit architecture
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Variable cache for instructions and data
Memory management unit
Typical computing power of 740 MIPS at 532-665 MHz
Also support Jazelle
Includes Thumb-2 technology
• Handle bit manipulation, table branches, conditional executions
– Includes Vector Floating Point (VFP) technology
• Single and double precision floating point computations
• Very useful in image processing applications, 2D and 3D transforms,
font generation, digital filters
• Popular devices using this microprocessor
– Apple’s iPhone and iPod Touch, Motorola’s RIZR
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The Cortex Family
• Utilizes the ARMv7 architecture, which comes in three flavors
• ARMv7-A
– Designed to support sophisticated, virtual memory-based OS and
user applications
– Includes NEON technology to support high-performance, media
intense applications such as video encoding/decoding, 3D
graphics, speech and image processing, and the like
• ARMv7-R
– Designed for real-time systems
• ARMv7-M
– Optimized for microcontroller and low-cost applications
• ARMv7 R and M also include VFP and dynamic compiler
support for just-in-time (JIT) dynamic adaptive (DAC) and ahead
of time (AOT) compilations
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Digital Signal Processors
• Included in cellular phones to improve their performance
• Optimized processors to handle computationally intensive and
repetitive mathematical operations quickly
– Fast Fourier Transforms, compression, and coding/decoding
algorithms
• Programmable, so different algorithms can be implemented with
the same chip
• Texas Instruments is the world leader in the DSP market
• TI offers several DSP platforms
– DaVinci digital media processors
– The series C5000 of low power DSPs
– The series C6000, the most recent family of high performance
• The TI series C6000 implements separate instruction and data caches
as well as an 8 MB 2nd level cache. These models are capable of as
many as 8000 MIPS, use very long instruction word (VLIW) encoding,
and perform eight operations per clock-cycle
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GPS Receiver
• Key hardware component in mobile-based location provider
architectures
– No GPS receiver, no GPS fixes!
• GPS receiver accuracy and energy consumption should be
carefully assessed by the application service provider
– Different chips provide different levels of accuracy, which may not
meet the application’s requirements
– Energy consumption is also a concern, as pinging the GPS receiver
and transmitting the fixes over the network may drain your phone’s
battery very fast
• New receivers with parallel, hardware correlator architectures
are coming. They will provide:
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Faster satellite signal acquisition
Higher sensitivity
More accurate fixes
Lower power consumption
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Memory
• Read Only Memory (ROM)
– Store programs on a permanent fashion
– ROM capacity in cell phones usually in the order of 64 Mb
– Information not affected by lack of power
• Random Access Memory (RAM)
– Read and write
– Information is volatile if power is switched off or not refreshed
periodically
– RAM capacity usually in the order of 128 Mb or more
• Two types of RAM
– Static and dynamic
• Static RAM (SRAM)
– Does not need to be refreshed
• Fast and power efficient but expensive
• Used to improve system’s performance as intermediate storage (cache)
where small amounts but fast access is needed for frequently used data
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Memory
• Dynamic RAM, or DRAM
– Cheaper than SRAM but slower and energy hungry, as it needs to be
refreshed
– Mainly used as main memory in computers
• Another type of non-volatile memory widely used in mobile
devices: Flash memory
– Two flavors: NOR and NAND flash memory
• NOR-based flash memory has long erase and write times but
provides full address and data buses
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Allows random access to any memory location
Excellent read time (comparable to RAM)
Suitable as a ROM replacement
Endurance between 10,000 and 1,000,000 erase cycles
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Memory
• NAND-based flash memory
– Faster erase and write time than NOR flash
– Up to 10 times better endurance
– High random access times
• Can’t address memory locations individually; must read in blocks
– Good for secondary storage, such as a hard drive
– microSD cards with capacities from 64 to 32 MB are common
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Future Trends and Challenges
• New multimedia and communication capabilities have called for
more computing power
• But, without increasing, or perhaps reducing, energy
consumption, size, and cost
• Integrating more smaller and more energy-efficient transistors
was the solution in the past
– As integration increased considerably, so it did power consumption
• Recall that Power ~ C V2f
– Reducing frequency of operation f is an option but makes the chip
slower
– Reducing the voltage of operation reduces the power in a quadratic
manner
• This trend has been pursued by chip manufactures aggressively
– Lower voltages of operation and different modes of operation,
e.g., sleep modes, are currently available in most chips inside
battery powered devices, such as laptops and cell phones.
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Future Trends and Challenges
• New solutions are needed because integration of more and
more transistors per area continues
• One option is parallelism
– Assume that at V1, the chip works at f1
– If voltage is divided by half, the frequency is also divided by half,
but the power is now reduced to one eighth
• At the expense of having a chip that is twice slower
– If we add another chip to make up for the computational power lost,
the two chips will have the same computational power while saving
power by a factor of four
• Therefore, power savings can be achieved by multiple (parallel)
processors
• New challenges are also introduced such as performing operations in
parallel in an efficient manner
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Software Architecture
• Cellular phones, as any other computer, contain three layers of
software
– Application-level software
• Programs running in the device that are meaningful to the user
– Middleware software
• Interfaces that automate widely used tasks, e.g., APIs
• Shorten the software development time and reduce programming errors
– Low-level software
• OS, drivers, and virtual machines
• Virtual machines
– Additional software layer on top of the operating system that also
executes computer programs
– Make the applications operating system independent allowing real
portability of applications among computers
– Virtual machines offer applications the same services and interfaces
and hide the particularities of each operating system
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The Java ME Virtual Machine
Java
Source
(*.java)
• The Java Virtual Machine
(JVM) is in charge of the
execution of compiled
programs that generate Java
bytecode
• The JVM consists of
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Execution engine
Heap
Garbage collector
Loader
Verifier
Thread manager
Java Compiler
Java
Bytecode
(*.jar)
Java Virtual Machine
Operating System
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The Java KVM
Global
variables
(program
counter, stack
pointer, frame
pointer,
others)
Methods Area
Execution Engine
JVM Stacks
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The Execution Engine
• Module that executes the Java bytecode
– Similar to low-level machine languages
• Operational codes and operands
– 200 standard bytecodes
• Load, store, arithmetic functions. Type conversions, push and pop stack
operations, branching, etc.
• Can be implemented as an interpreter, compiler, or Java processor
– Interpreter is a processor emulated in software
• Reads source code written in a high-level language, transforms it into
machine code, and executes the machine code
• Speed is the main issue, as it takes longer to run an interpreted program
– The choice for resource-constrained devices
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The Execution Engine
• Java compilers compile Java bytecode into machine language
– Code is run in the hardware as any other compiled program
– Static Compilation before program is run
• Usual procedure
• High quality code
• Does not allow dynamic class loading and only runs on a specific
machine
– Dynamic Compilation at runtime
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Dynamic class loading allowed
Runs on any machine
Speed depends on amount of methods that are repeatedly run
Interpreting and executing is faster than compiling and executing
• Java processors implement the JVM in hardware
– Bytecodes are the instruction set of the machine
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The Heap
• Memory area used by the JVM to store data and code during
runtime
– The methods area stores the methods to be executed
• Permanent area; outside the scope of the garbage collector
– The stack
• JVM is stack-based; all operations are done through a stack
• One stack per thread
• Each stack consists of frames where local variables and operands to
execute a method are stored
• One frame can be active at any given time
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The Garbage Collector
• Module in charge of claiming the memory space occupied by
objects that are no longer referenced by the program
• Liberates the programmer from this tasks
• May introduce a performance penalty, which may vary
depending on the algorithm used
• The GC included in the KVM is a simple, non-moving, singlespace, mark-and-sweep garbage collectors
– Marks referenced objects and sweeps unmarked ones
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The Loader
• Module in charge of loading the application’s class files
• Called at the beginning of the execution or dynamically
• For security reasons, a conforming VM for resource-constrained
devices does not support user-defined loaders
– A built-in “bootstrap” class loader that cannot be overridden,
replaced, or reconfigured is used
– Loads main classes (CLDC and MIDP), Optional APIs, and MIDlet
Java Archive (JAR) files
– A Java application can load application classes only from its own
JAR file. This restriction ensures that Java applications on a device
cannot interfere with each other or steal data from each other
• This means that the only classes that can be linked and loaded at
runtime are those that come from the same jar file, therefore
dynamically linking classes from another .jar file in Java ME is not
possible
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The Verifier
• Checks if the loaded bytecode can be safely run in the VM
– Typos, stack overflow, correct branching, etc.
• Verifier included in the Java SE VM is too big and requires too
much CPU power to run these algorithms in real-time
– Not good for resource-constrained devices
• Verification process in resource-constrained devices in 2 steps
– Offline pre-verification in developer’s workstation
• Includes tags (StackMap)
– Verification at runtime using the tags
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The Thread Manager
• Java supports multi-threading
• Thread manager coordinates the execution of the threads
• Java KVM does not support thread groups
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